12 Commits

Author	SHA1	Message	Date
Thomas Harte	d910405648	Added enough infrastructure to be able to react to the two CP/M calls this cares about.	2017-05-19 21:53:39 -04:00
Thomas Harte	62b432c046	Added the concept of a trap handler to the all-RAM processor and exposed it via the test Z80 classes.	2017-05-19 21:20:28 -04:00
Thomas Harte	64d6ee1be5	Adjusted slightly to adapt to latest Swift warnings.	2017-05-17 07:49:48 -04:00
Thomas Harte	87a021ec2d	Made further attempt to get as fas as having the Z80 attempt to do something.	2017-05-16 22:19:40 -04:00
Thomas Harte	189317b80c	Added enough of a Z80 test machine to bridge up into Swift.	2017-05-16 22:05:42 -04:00
Thomas Harte	df80c37adb	Renamed TestMachine to TestMachine6502 since there's going to be multiple of them.	2017-05-15 08:18:57 -04:00
Thomas Harte	0808e9b6fb	Pulled the 6502 into a CPU namespace, making it an instance of something that has micro-opcodes and schedules them, and factoring out the formulation of a register pair.	2017-05-14 22:08:15 -04:00
Thomas Harte	d1fe07f14d	Added test of perfect DPLL input timing.	2016-07-12 21:42:23 -04:00
Thomas Harte	d8334edf4a	Started trying to clean up, including commuting the C1540 source file name to match its class name but mainly by adding documentation.	2016-07-10 07:46:20 -04:00
Thomas Harte	66caa3c6dc	Fixed setup of bridge class.	2016-07-09 17:23:43 -04:00
Thomas Harte	bf03985ea4	Here's an instantly failing test...	2016-07-09 17:22:10 -04:00
Thomas Harte	865eb421cd	Quick on-disk tidy up.	2016-07-09 15:44:55 -04:00