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mirror of https://github.com/TomHarte/CLK.git synced 2024-11-26 23:52:26 +00:00
Commit Graph

21 Commits

Author SHA1 Message Date
Thomas Harte
7cf6008e7c Started some very basic RIOT unit tests; corrected to pass. 2016-06-19 20:12:47 -04:00
Thomas Harte
f4915c5ad6 Fixed test and added basic implementation of data direction. 2016-06-18 17:17:03 -04:00
Thomas Harte
eea850cd12 Added a deliberately failing data direction test. 2016-06-18 16:40:01 -04:00
Thomas Harte
2282b59768 Added a quick latching test, and shortened test messages, albeit that they're still displeasingly boilerplate. 2016-06-18 16:10:46 -04:00
Thomas Harte
5d26cd85a3 Wrote test case for what appears to be correct timer behaviour if those were acting in isolation. Ensured implementation matches test case. 2016-06-18 14:30:23 -04:00
Thomas Harte
394902f409 Switched to clocking the 6522 by the half-cycle. Very trivial test now passes. 2016-06-18 13:57:10 -04:00
Thomas Harte
06fb2ff1c7 Started endeavouring to sketch out the boilerplate for writing a 6522 test harness. Added a default implementation of synchronise to the 6522 too, since not everybody is going to want one. 2016-06-18 09:28:46 -04:00
Thomas Harte
9b64f64db7 Attempted to normalise some style decisions.` 2016-04-24 22:32:24 -04:00
Thomas Harte
675070c5dd Very, _very_ minor: switched to normal C++ constructor syntax for simple variable initialisation. 2015-12-06 16:53:37 -05:00
Thomas Harte
cc98534f94 Added test for NOP, discovering the undocumented ones to be the incorrect length. 2015-08-13 07:32:50 +01:00
Thomas Harte
6616265d93 Fixed collision tests, added a few more timing tests. 2015-08-13 03:33:45 +01:00
Thomas Harte
dd0f17130a Found and fixed some timing errors in absolute indexed and in (indirect), y addressing modes: neither is able in write or read-modify-write modes to shave a cycle as then can when reading. 2015-08-13 02:58:39 +01:00
Thomas Harte
975836c30f Added a quick snippet test, discovering that I've cut a cycle from read/modify/writes. 2015-08-13 02:18:41 +01:00
Thomas Harte
503d684af0 Added a couple of timing tests, both of which seem to pass for now. 2015-08-13 01:55:23 +01:00
Thomas Harte
e8f70398c1 Added one basic timing test, for now: implied nop should be two cycles. 2015-08-13 01:06:56 +01:00
Thomas Harte
d19f8ed507 Removed the implicit reset upon 6502 startup, adding a reset line. Hence all tests now pass again. Added an empty shell for timing tests, the all-RAM 6502 now counting bus cycles. 2015-08-13 00:51:06 +01:00
Thomas Harte
53dd5c8f16 Trying to fix my RDY line emulation. Switched to PAL timings, at least temporarily, since it's starting to make a difference. 2015-07-31 16:44:53 -04:00
Thomas Harte
20c2d98b9a Converted remaining spaces to real tabs. 2015-07-30 20:51:32 -04:00
Thomas Harte
6252f6030f Switched to idiomatic source name, ensured latest project name is in all appropriate header places, threw texture coordinates slightly into the shader mix. 2015-07-26 15:25:11 -04:00
Thomas Harte
5160b6bbb8 Separated out different test suites into different XCTest subclasses. 2015-07-16 20:52:16 -04:00
Thomas Harte
24c0579b94 Shuffled things and guessed at things until the Xcode project was happy being subservient to the project proper. 2015-07-16 20:27:31 -04:00