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Commit Graph

9158 Commits

Author SHA1 Message Date
Thomas Harte
76814588b8 Template Instruction on its content size. 2022-02-21 12:36:03 -05:00
Thomas Harte
1934c7faa2 Switch Decoder into a template. 2022-02-21 12:21:57 -05:00
Thomas Harte
9e9e160c43 Eliminate Ind[BXPlusSI/etc] in favour of specifying everything via a ScaleIndexBase. 2022-02-21 11:45:46 -05:00
Thomas Harte
546b4edbf1 Ensure ScaleIndexBase can be used constexpr; add note-to-self on indexing table. 2022-02-20 19:22:28 -05:00
Thomas Harte
63d8a88e2f Switch to holding the SIB as a typed ScaleIndexBase.
(and permit copy assignment)
2022-02-20 17:54:53 -05:00
Thomas Harte
75d2d64e7c Albeit that it requires nuanced shift/roll semantics, eliminates CL constant.
Shifts and rolls are already slightly semantically special for being undefined for values greater than 8/16/32 — i.e. in some implementations they don't even use the entirety of CL, just the low five bits. Which makes me feel a little better.

The upside of no ambiguity between eCX size 1 and CL justifies the trade.
2022-02-20 17:52:19 -05:00
Thomas Harte
a5113998e2 Accept that IN and OUT are going to have special semantics, thereby kill ::AX and ::DX. 2022-02-20 17:15:01 -05:00
Thomas Harte
4d2e8cd71d Adds a presently-unreachable step for SIB consumption. 2022-02-19 18:00:27 -05:00
Thomas Harte
30b355fd6f Chips away further at the legacy register names. 2022-02-18 18:37:47 -05:00
Thomas Harte
c257b91552 Update tests to preference away from [A/B/C/D]L. 2022-02-18 16:32:28 -05:00
Thomas Harte
12df7112da Starts adjusting the concept of a Source. 2022-02-17 11:32:09 -05:00
Thomas Harte
cd5ca3f65b Attempts a full decoding of the 80286 instruction set. 2022-02-10 17:13:50 -05:00
Thomas Harte
0bd63cf00f Introduces the easy F page instructions. 2022-02-10 09:35:05 -05:00
Thomas Harte
7ceb3369eb Attempts decoding of the 80186 set. 2022-02-09 17:51:48 -05:00
Thomas Harte
ae21726287 Splits 80186 additions from 80286; fills in a touch more. 2022-02-01 20:38:10 -05:00
Thomas Harte
a4da1b6eb0 Begins enumerating the 80286 and 80386 instructions. 2022-01-31 09:11:06 -05:00
Thomas Harte
85bfd2eba3 Remove further errant 'Awaiting's. 2022-01-31 08:22:07 -05:00
Thomas Harte
2d543590dc Make a noun, for better consistency. 2022-01-31 08:14:33 -05:00
Thomas Harte
55dbeefeb2
Merge pull request #1005 from TomHarte/SerialPort
Adds empty callouts for all serial port registers.
2021-12-25 16:39:27 -05:00
Thomas Harte
4d9589af7c
Merge pull request #1006 from TomHarte/Shared68000Tables
Minor 68000 style improvements.
2021-12-25 14:11:25 -05:00
Thomas Harte
ee625cb8a8 Minor style improvements; especially: don't assume value of NoBusProgram. 2021-12-25 14:05:38 -05:00
Thomas Harte
f20940a37b Give Program full ownership of the sentinel value.
In case I want to reduce the size of this field later.
2021-12-23 16:32:21 -05:00
Thomas Harte
32e0a66610 Trust the compiler with this bit field. 2021-12-23 16:28:55 -05:00
Thomas Harte
d9598b35c2 Add some additional metrics. 2021-12-23 16:27:54 -05:00
Thomas Harte
acba357df6 Adds empty callouts for all serial port registers. 2021-12-23 15:22:20 -05:00
Thomas Harte
7ce335d9da
Merge pull request #1004 from TomHarte/FastRAM
Adds fast RAM to the Amiga, along with size selection for both fast & chip.
2021-12-23 11:43:42 -05:00
Thomas Harte
3caf9ca914 Remove a bunch of unused names. 2021-12-23 11:39:00 -05:00
Thomas Harte
fd569201ef Add Qt GUI for Amiga memory selection. 2021-12-23 11:28:44 -05:00
Thomas Harte
f094aa946a Add Mac GUI for Amiga memory selection. 2021-12-22 18:20:55 -05:00
Thomas Harte
a17c192a9e Allow chip RAM size selection, while I'm here. 2021-12-22 15:30:19 -05:00
Thomas Harte
1916a9b99c Remove stdout noise. 2021-12-22 15:22:28 -05:00
Thomas Harte
9796b308dc Add basic implementation of fast RAM. 2021-12-22 15:17:11 -05:00
Thomas Harte
bdf0a1941c
Merge pull request #1002 from TomHarte/FastBlitterFills
Switch to a table-based implementation of fill mode.
2021-12-19 17:35:27 -05:00
Thomas Harte
d0e3024bec Switch to nibble-oriented lookup tables for fill mode. 2021-12-19 17:16:46 -05:00
Thomas Harte
d2ad149e56 Fill mode always runs right to left. 2021-12-19 16:43:18 -05:00
Thomas Harte
ad602a4722
Merge pull request #1001 from TomHarte/AmigaReadWrite
Ensures Chipset reads can map to writes and vice versa.
2021-12-19 16:35:43 -05:00
Thomas Harte
348840a2aa It's probably a net detriment to use a template in this scenario. 2021-12-19 16:31:44 -05:00
Thomas Harte
3a719633eb Consolidate interface; correct LOGs. 2021-12-18 19:39:41 -05:00
Thomas Harte
bd69948d37 The Copper can now skip Chipset::perform. 2021-12-18 17:53:11 -05:00
Thomas Harte
54aa211f56 Avoid infinite loops for completely undefined addresses. 2021-12-18 17:48:45 -05:00
Thomas Harte
f118891970 Breaks Chipset::perform into read and write.
This allows each to call the other when a read occurs of a write-only address, and vice versa.
2021-12-18 17:43:53 -05:00
Thomas Harte
c4055fde97
Merge pull request #1000 from TomHarte/CopperTests
Amiga: regularises timing; improves Copper sleep/wait costs
2021-12-18 16:46:53 -05:00
Thomas Harte
dbae3fc9a5 Propagate to bitplanes immediately; fix odd/even confusion. 2021-12-18 16:37:40 -05:00
Thomas Harte
7c73ed7ed5 Bump Xcode version number. 2021-12-18 14:55:27 -05:00
Thomas Harte
c834960bfb Withdraw separate x-and-y guess, make MOVE lose a cycle if a sleep/wake occurs. 2021-12-12 19:18:18 -05:00
Thomas Harte
600abc55b5 Compare x and y separately, wake immediately from a sleep, log more. 2021-12-12 17:26:33 -05:00
Thomas Harte
f3ec7d54bb Clarifies wait-for-CPU-slot semantics.
Big bonus: this guarantees `advance_dma`s will be called at most once per output cycle, even if they return `false`.
2021-12-09 19:17:44 -05:00
Thomas Harte
090760e526
Merge pull request #998 from TomHarte/QtAmiga
Add the Amiga to the Qt UI.
2021-12-08 13:45:34 -05:00
Thomas Harte
cccde7dc89 Correct given memory size. 2021-12-08 11:41:50 -05:00
Thomas Harte
849e48f519 Add the Amiga to Qt's UI. 2021-12-08 11:41:38 -05:00