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11,837 Commits 10 Branches 121 Tags 500 MiB
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1389 Commits

Author SHA1 Message Date
Thomas Harte
49c811b5f5 Avoid taking an out-of-range pointer. 
(Even though it was safe)
 2024-10-19 10:12:51 -04:00
Thomas Harte
02f92a7818 Handle runs that don't cross a pixel boundary. 
`
 2024-10-15 21:15:30 -04:00
Thomas Harte
a9c8ef642c Correct original author's typo. 2024-08-14 18:55:35 -04:00
Thomas Harte
30b1b36e63 Test digits individually; CSLs autolink. 2024-08-07 22:44:48 -04:00
Thomas Harte
2d049f5fdc Implement reset, correct file names. 2024-08-07 22:00:24 -04:00
Thomas Harte
05f0a122f4 Blank out border. 2024-08-05 22:06:23 -04:00
Thomas Harte
1977675a73 Add some measure of graphics output. 2024-08-05 21:48:40 -04:00
Thomas Harte
4ceaab7c26 Merge branch 'master' into SSLandCSL 2024-07-26 22:08:11 -04:00
Thomas Harte
76ca607021 Add a graceful end for JAM. 2024-07-26 21:45:17 -04:00
Thomas Harte
78b2a89554 Add header for std::vector. 2024-07-08 00:20:54 +02:00
Thomas Harte
dbc0ecde31 Catch SSM events. 2024-06-30 21:26:16 -04:00
Thomas Harte
0e30e2d865 Add CSL side of execution. 2024-06-30 20:19:02 -04:00
Thomas Harte
ba1879ef78 Add URL credit. 2024-06-28 21:53:18 -04:00
Thomas Harte
7a145d72f9 Start Shaker test case. 2024-06-28 21:52:04 -04:00
Thomas Harte
5280f5aba2 Attempt to spot screen takeovers. 2024-05-23 22:03:40 -04:00
Thomas Harte
67add0da93 Use both sources. 2024-05-21 22:23:53 -04:00
Thomas Harte
6d6dfa4f44 Introduce Archimedes analyser tests. 2024-05-20 22:48:20 -04:00
Thomas Harte
7d8a364658 Reimplement LDM and STM. 2024-04-04 21:59:18 -04:00
Thomas Harte
8a6bf84cff Keyboard: log more, ignore unrecognised commands. 2024-03-29 20:54:07 -04:00
Thomas Harte
bb339d619f Eliminate trace test; I don't think I'm going to work it through. 2024-03-28 14:23:00 -04:00
Thomas Harte
2ed11877e8 Determine a couple of further exclusions. 2024-03-28 14:11:41 -04:00
Thomas Harte
ea6b83815b Add a further category of exclusions. 2024-03-28 14:01:37 -04:00
Thomas Harte
740b0e35d5 Completely bypass ignored tests. 2024-03-28 11:28:37 -04:00
Thomas Harte
4fcb85d132 Cleave off most remaining reasons for failure. 2024-03-28 10:32:27 -04:00
Thomas Harte
c04c708a9d Trade some depth for breadth. 2024-03-27 22:37:10 -04:00
Thomas Harte
f4cf1e5313 Attempt to cleave by broad reason. 2024-03-27 22:36:37 -04:00
Thomas Harte
3549488b7a Add round-trip test for status flags. 2024-03-24 22:18:16 -04:00
Thomas Harte
2ad6bb099b Begin foray into disassembly. 2024-03-19 11:34:10 -04:00
Thomas Harte
3a899ea4be Add test coverage for STM descending, proving nothing. 2024-03-15 14:55:17 -04:00
Thomas Harte
e7457461ba Reduce magic constants. 2024-03-11 14:49:03 -04:00
Thomas Harte
ca779bc841 Expand test set. 2024-03-11 14:48:18 -04:00
Thomas Harte
db49146efe Figure out what's going on with TEQ. 2024-03-11 09:51:09 -04:00
Thomas Harte
830d70d3aa Trust tests on immediate-opcode ROR 0; limit shift by register. 2024-03-10 23:38:31 -04:00
Thomas Harte
336292bc49 Further correct R15 as a destination. 2024-03-10 22:56:02 -04:00
Thomas Harte
bd62228cc6 The test set doesn't seem to do word rotation. 2024-03-10 22:40:37 -04:00
Thomas Harte
ccdd340c9a Reads also may or may not be aligned. *sigh* 2024-03-10 22:34:56 -04:00
Thomas Harte
0b42f5fb30 Make further test-set allowances. 2024-03-10 22:29:40 -04:00
Thomas Harte
21278d028c Correct unaligned accesses. 2024-03-10 21:56:19 -04:00
Thomas Harte
fbc273f114 Add invented model for tests. 2024-03-10 21:45:56 -04:00
Thomas Harte
06a5df029d Summarise failures. 2024-03-10 16:56:39 -04:00
Thomas Harte
e17700b495 Permit digression for 03110002, temporarily. 2024-03-10 14:47:02 -04:00
Thomas Harte
655b1e516c Test PSR and PC. 2024-03-10 14:14:18 -04:00
Thomas Harte
4e7a63f792 Do a de minimis checking of memory accesses. 2024-03-09 15:18:35 -05:00
Thomas Harte
a2896b9bd0 Test register values. 2024-03-09 15:11:12 -05:00
Thomas Harte
d6f882a8bb Integrate PC and PSR, guarantee invisible register values. 2024-03-09 14:59:44 -05:00
Thomas Harte
08f50f3eff Box in flags. 2024-03-08 23:01:29 -05:00
Thomas Harte
47f7340dfc Start hacking in some ARM tests. 2024-03-08 22:54:42 -05:00
Thomas Harte
9406a97141 Add some register switch tests. 2024-03-08 11:34:10 -05:00
Thomas Harte
0d666f9935 Get a bit more rigorous about reporting. 2024-03-06 09:54:39 -05:00
Thomas Harte
230e9c6327 Obscure active. 2024-03-03 21:43:30 -05:00