47 Commits

Author	SHA1	Message	Date
Thomas Harte	8a8c044976	Support up to 15 extension words on a Preinstruction; use that to describe PACK/UNPK. ... TODO: reconcile when to use that field versus the ExtensionWord operand. Probably only when operands are full?	2022-10-28 13:36:40 -04:00
Thomas Harte	8ff9f27b91	Decode MOVES.	2022-10-26 13:34:01 -04:00
Thomas Harte	ae2419e283	Decode MOVEC.	2022-10-26 12:50:15 -04:00
Thomas Harte	7ba6c78d14	MOVE from CCR, MOVEC and MOVES are on the 68010.	2022-10-25 21:27:23 -04:00
Thomas Harte	d8a11eaba7	Avoid explicit specialisation in non-namespace scope.	2022-10-25 10:13:12 -04:00
Thomas Harte	38c531fd5a	Accept that a uint8_t isn't always going to be large enough; split decoding by minimum processor.	2022-10-25 09:50:19 -04:00
Thomas Harte	8c670d2105	Add decodes for TRAPcc and PACK, discovering it's three operand (sort of).	2022-10-23 11:46:47 -04:00
Thomas Harte	9a56d053f8	Introduce/extend 68k enums to cover 68020 instruction set.	2022-10-22 15:20:30 -04:00
Thomas Harte	cb0e259339	Start the process of decoding 68020 operations.	2022-10-21 15:28:29 -04:00
Thomas Harte	72b6ab4389	Provide a route to operation that factors in addressing mode.	2022-09-06 11:26:16 -04:00
Thomas Harte	effe8c102d	Provide a direct to_string on Operation.	2022-09-05 21:52:20 -04:00
Thomas Harte	8ada73b283	Use the outer switch for addressing mode dispatch, saving a lot of syntax.	2022-06-13 08:57:49 -04:00
Thomas Harte	73815ba1dd	No need for this hoop jumping here.	2022-06-01 08:20:06 -04:00
Thomas Harte	3da720c789	Make requires_supervisor explicitly compile-time usable.	2022-05-29 14:55:24 -04:00
Thomas Harte	eeb6a088b8	Add a tag to avoid duplication.	2022-05-19 15:49:42 -04:00
Thomas Harte	c6c6213460	Bifurcate the fetch-operand flow. ... Address calculation will be the same, but the fetch will differ. I don't think there's a neat costless way to factor out the address calculations, alas, but I'll see whether macros can save the day.	2022-05-19 10:27:51 -04:00
Thomas Harte	4299334e24	Clean up some TODOs, eliminate one further conditional.	2022-05-13 11:17:57 -04:00
Thomas Harte	5b67c9bf4a	MOVE to SR requires supervisor privileges.	2022-05-13 09:01:03 -04:00
Thomas Harte	2fa6b2301b	Move string logic into Preinstruction.	2022-05-12 19:46:08 -04:00
Thomas Harte	7445c617bc	Start removing 68000-specific timing calculations.	2022-05-09 20:32:02 -04:00
Thomas Harte	8e5650fde9	Clean up Instruction.hpp.	2022-05-09 10:13:42 -04:00
Thomas Harte	98cb9cc1eb	Fix CHK operand size.	2022-05-07 21:16:44 -04:00
Thomas Harte	2b3900fd14	Fix LINK A7.	2022-05-07 08:15:26 -04:00
Thomas Harte	1defeca1ad	Implement RTS, RTR, RTE.	2022-05-06 12:30:49 -04:00
Thomas Harte	8176bb6f79	Expose issues with TST and TAS.	2022-05-06 12:18:56 -04:00
Thomas Harte	607ddd2f78	Preserve MOVEM order in Operation.	2022-05-06 09:45:06 -04:00
Thomas Harte	fed79a116f	Be overt about the size being described here.	2022-05-06 09:22:38 -04:00
Thomas Harte	d7d0a5c15e	Implement MOVEM to memory.	2022-05-05 18:51:29 -04:00
Thomas Harte	9ab70b340c	Route MOVEM appropriately.	2022-05-05 12:42:57 -04:00
Thomas Harte	f63a872387	BTST does not write back.	2022-05-05 12:32:15 -04:00
Thomas Harte	665f2d4c00	Attempts MOVEP.	2022-05-05 09:00:33 -04:00
Thomas Harte	64586ca7ba	Implement BTST/etc.	2022-05-04 20:57:22 -04:00
Thomas Harte	15c90e546f	Fix rotates and shifts to memory.	2022-05-04 19:44:59 -04:00
Thomas Harte	5aabe01b6d	Mostly fix LINK and UNLK.	2022-05-04 08:41:55 -04:00
Thomas Harte	7d10976e08	Add LINK and UNLINK to operand_flags.	2022-05-03 20:51:02 -04:00
Thomas Harte	d3b55a74a5	Fix LEA, proceed to non-functional LINK and UNLK.	2022-05-03 20:45:36 -04:00
Thomas Harte	052ba80fd7	Add enough wiring to complete but fail EXT and JMP/JSR.	2022-05-03 15:49:55 -04:00
Thomas Harte	39f0ec7536	Get far enough through CHK to realise that MOVEM probably needs to be divided by direction.	2022-05-03 15:40:04 -04:00
Thomas Harte	af973138df	Correct decoding of Bcc.b, satisfying Bcc and BSR tests.	2022-05-03 15:32:54 -04:00
Thomas Harte	90f0005cf2	Proceed to failing Bcc and flagging up my lack of an implementation for BSR.	2022-05-03 14:45:49 -04:00
Thomas Harte	d8b3748d24	Fix Scc size, DBcc behaviour.	2022-05-03 14:40:51 -04:00
Thomas Harte	1b224c961e	Fix Scc, add operand flags for DBcc.	2022-05-03 14:23:57 -04:00
Thomas Harte	b3cf13775b	Consume operand_flags into Instruction.hpp.	2022-05-03 11:09:57 -04:00
Thomas Harte	6b073c6067	Attempt to round out addressing modes, shift to a header, as per templating on BusHandler.	2022-05-01 15:10:54 -04:00
Thomas Harte	42927c1e32	Establish more of the 680x0 executor loop.	2022-05-01 13:00:20 -04:00
Thomas Harte	8d24c00df2	Include decoded condition in Preinstruction.	2022-04-30 09:00:47 -04:00
Thomas Harte	9cbbb6e508	Adjust path to match namespace; add to Qt project.	2022-04-27 08:05:36 -04:00