18 Commits

Author	SHA1	Message	Date
Thomas Harte	5f030edea4	Simplify transaction.	2022-05-26 19:37:30 -04:00
Thomas Harte	88e33353a1	Fix instruction and time counting, and initial state.	2022-05-26 09:17:37 -04:00
Thomas Harte	f3c0c62c79	Switch register-setting interface.	2022-05-26 07:52:14 -04:00
Thomas Harte	866787c5d3	Make an effort to withdraw from the high-circuitous stuff of working around the reset sequence.	2022-05-25 20:22:38 -04:00
Thomas Harte	64491525b4	Work further to guess at caller's intention for set_state. ... Probably I should just eliminate the initial reset, somehow.	2022-05-25 17:01:18 -04:00
Thomas Harte	68b184885f	Reapply only the status.	2022-05-25 16:54:25 -04:00
Thomas Harte	06f3c716f5	Make better effort to establish initial state.	2022-05-25 16:47:41 -04:00
Thomas Harte	22714b8c7f	Capture state at instruction end, for potential inspection.	2022-05-25 16:32:26 -04:00
Thomas Harte	f9d1c554b7	Fix for the actual number of cycles in a standard reset.	2022-05-25 16:05:28 -04:00
Thomas Harte	463fbb07f9	Adapt remaining 68000 tests to use Mk2.	2022-05-25 10:55:17 -04:00
Thomas Harte	e402e690b0	Assume and test that divide-by-zero posts the PC of the offending instruction.	2021-08-07 17:51:00 -04:00
Thomas Harte	8641494809	Resolve various test-case warnings.	2020-09-27 15:10:29 -04:00
Thomas Harte	6595f8f527	Introduces a timing test for LSL. Which already passes.	2020-01-08 22:35:28 -05:00
Thomas Harte	617e0bada9	Adds some minor extra testing. Highly duplicative, to be honest.	2020-01-02 23:14:05 -05:00
Thomas Harte	1c154131f9	Expands size of storage in Cycles/HalfCycles; adjusts widely to compensate.	2019-10-29 22:36:29 -04:00
Thomas Harte	d30e7504c2	Factors out MOVE tests, and ensures test machine RAM is zero initialised.	2019-06-30 21:43:30 -04:00
Thomas Harte	8d0cd356fd	Corrects TRAP, TRAPV and CHK timing.	2019-06-29 21:25:22 -04:00
Thomas Harte	7cc91e1bc5	Factors the bitwise tests out of the main bundle, as that pushes up towards 6,000 lines.	2019-06-28 21:58:38 -04:00