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733 Commits

Author SHA1 Message Date
Thomas Harte
31b048f966 Ensures all bools start in a valid state. 2018-09-10 22:21:03 -04:00
Thomas Harte
7b9c1bb69c Makes minor layout improvements. 2018-09-09 21:02:31 -04:00
Thomas Harte
70c4d6b9b3 Adds a one second delay between controller and drive motor off. 2018-08-03 21:13:18 -04:00
Thomas Harte
98bb5bd9f1 Ensures flux bits are observable for two cycles rather than one; it should be 1us. 2018-07-31 23:01:11 -04:00
Thomas Harte
92065813ef Ensures only the first 8px of sprites is output in 8x8 mode. 
Also adds a little extra documentation.
 2018-07-15 22:21:29 -04:00
Thomas Harte
cd464fc7de Corrects status logging. 2018-06-26 20:53:08 -04:00
Thomas Harte
df8c896193 Removes unused state and implements AND output readback. 2018-06-26 19:31:16 -04:00
Thomas Harte
59f8eeb05a Ensures the AY goes high impedance when not in read mode. 2018-06-25 20:48:24 -04:00
Thomas Harte
5ab4cfee84 Factors out repeated hex-size setting. 2018-06-21 19:27:54 -04:00
Thomas Harte
a9eb0d02c6 Returns sanity to 8272 logging. 2018-06-20 23:02:32 -04:00
Thomas Harte
adca862166 Finally makes an initial pass at logging macros. 2018-06-18 22:37:19 -04:00
Thomas Harte
dde9b73a22 Creates the through-path that will be necessary for RWTS acceleration. 2018-06-09 12:51:53 -04:00
Thomas Harte
076fa55651 Corrects: flux set is no-flux incoming. 
This restores good sleeping behaviour.
 2018-06-03 08:11:17 -04:00
Thomas Harte
1a9cea050e Minor: ensure AY registers *read* as 0 from reset, as well as being 0. 2018-06-01 19:48:42 -04:00
Thomas Harte
35e84ff1a8 Corrects NTSC quadrature phase. 2018-05-31 21:40:46 -04:00
Thomas Harte
75f9e3caeb Resolves incorrect bracketing. 2018-05-28 17:48:35 -04:00
Thomas Harte
928aab13dc Introduces more granular clocking announcements to the Disk II. 
As well as making it accept the clock rate it'll actually receive, to supply to the drives, so that they spin at the proper speed.
 2018-05-28 17:19:29 -04:00
Thomas Harte
db8d8d8404 Commutes Sleeper to ClockingHint::Source, making state more granular. 2018-05-27 23:17:06 -04:00
Thomas Harte
086b801c29 Mildly rearranges to avoid unnecessary call. 2018-05-22 21:50:07 -04:00
Thomas Harte
e482929da8 Enhances the Disk II's ability to sleep. 
Also enables Disk II sleep observation in the Oric.
 2018-05-19 23:15:28 -04:00
Thomas Harte
ed06533e60 Implements write support out of the Disk II. 2018-05-18 22:07:58 -04:00
Thomas Harte
7b7beb13a3 Eliminates the fiction of setting and getting registers. 
The Disk II seems lower level than that; it will read the data bus whenever it likes, it is the programmer's responsibility to keep up with that. It also reserves the right not to load the bus regardless of whether it receives a read or write access.
 2018-05-17 21:39:11 -04:00
Thomas Harte
c46007332a Switches to returning the shift register contents on every even read. 2018-05-17 20:18:34 -04:00
Thomas Harte
908d3b0ee5 Slightly wrong as to the details, but gets the controller trying to output. 
At an initial look, I think the shift register should end up on the data bus for all odd accesses. Need to investigate more thoroughly.
 2018-05-16 22:37:22 -04:00
Thomas Harte
8a031b1137 Eliminates 'data' register as it doesn't exist; rejigs state machine command set. 2018-05-16 22:09:59 -04:00
Thomas Harte
1aba9f807e Ensures proper upward propagation of sleeping from first start. 2018-05-16 22:07:54 -04:00
Thomas Harte
4c49963988 Switches to proper handling of the motor control and write protection. 
Per Understanding the Apple II the drive looks write protected  while phase 1 is enabled.
 2018-05-16 21:44:09 -04:00
Thomas Harte
ad9b0cd4e3 Eliminates all endashes. 2018-05-13 15:43:03 -04:00
Thomas Harte
5d6b5d9f10 Eliminates all emdashes in cross-platform code. 2018-05-13 15:34:31 -04:00
Thomas Harte
0b771ce61a Removes all instances of the copyright symbol. 2018-05-13 15:19:52 -04:00
Thomas Harte
d703328114 Adds missing #include for memcpy. 2018-05-12 17:54:13 -04:00
Thomas Harte
bc464e247f The 1540 and, by extension, the Vic-20 are now activity sources. 2018-05-11 22:24:33 -04:00
Thomas Harte
a43ca0db35 Makes the Apple II an activity source. 2018-05-10 22:17:13 -04:00
Thomas Harte
c3144382c5 Shuffles the Disk II ROM at load time into B.A.P. form. 
Only if required. In order to support various potential forms of supplied ROM.
 2018-05-09 22:03:59 -04:00
Thomas Harte
c3a2f7717b Makes attempt to implement support for the Pravetz 8D + 8DOS. 
i.e. the Disk II wired up to the Oric, with some ROM swaps.
 2018-05-08 22:05:43 -04:00
Thomas Harte
f65c65569a Makes disk head position explicitly something with sub-integral precision. 
Also as a drive-by fix, corrects accidental assumption of 10 sectors for all MFMSectorDump descendants.
 2018-05-06 23:17:36 -04:00
Thomas Harte
aacf26f05d Removed logged comment. 2018-04-30 22:03:09 -04:00
Thomas Harte
10c0e687f5 Attempts to introduce sleeping for the Disk II. 2018-04-29 17:51:10 -04:00
Thomas Harte
41075356e2 Makes a first attempt at NIB support. 2018-04-26 22:49:07 -04:00
Thomas Harte
d59db504a3 Adjusted stepper logic; some disks load now. 2018-04-25 21:59:18 -04:00
Thomas Harte
4c6dc597f4 Converts Time::get into a template, introduces a via-a-double fallback for the timed event loop. 2018-04-25 19:54:39 -04:00
Thomas Harte
7061537ff5 Makes joined-up attempt to run data through the Disk II. 2018-04-24 19:44:45 -07:00
Thomas Harte
99de8f1c5c Inverts the pulse strobe. 2018-04-24 09:03:03 -07:00
Thomas Harte
af61bbc3e2 Attempts actual performance of the state machine. 2018-04-24 08:29:05 -07:00
Thomas Harte
56d88f23ef Teeters closer and closer to trying actually to run the Disk II state machine. 2018-04-23 22:29:36 -07:00
Thomas Harte
4bff44377a Attempts to route Disk II requests to the thing itself. 2018-04-23 22:11:31 -07:00
Thomas Harte
e87a3cffd4 Merge branch 'master' into DiskII 2018-04-21 15:02:18 -07:00
Thomas Harte
5968c9a391 Corrects Apple II output audio. 2018-04-21 14:56:50 -07:00
Thomas Harte
72bc5f8d7b Adds a class to contain the Disk II and begins Apple GCR conversion routines. 2018-04-21 14:33:42 -07:00
Thomas Harte
f22c23cb4c Attempts to bring audio to the Apple II. 
By factoring the audio toggle out from the MSX.
 2018-04-17 22:28:13 -04:00
Thomas Harte
1c605d58e3 Removes the CRT requirement for an integral relationship between cycles and samples. 2018-04-16 20:00:56 -04:00
Thomas Harte
467cd5450f Adjusts PAL Vic timing. 2018-04-12 21:12:09 -04:00
Thomas Harte
428b6145fa Converts 6560 to more project normative templated form. 2018-04-11 22:00:42 -04:00
Thomas Harte
4c8a68c6a4 Implements late-0 with proper timing, and NTSC interlaced raster count timing. 2018-04-11 08:00:37 -04:00
Thomas Harte
0b4b6f4aec Tweaks luminances and reintroduces late-to-zero line counts. 2018-04-10 23:05:18 -04:00
Thomas Harte
cf6f6c5c15 Eliminates the full_frame_counter_ and slightly tweaks NTSC raster timing. 2018-04-08 18:51:20 -04:00
Thomas Harte
f541986333 Switches to more normative preincrement. 2018-04-08 18:50:42 -04:00
Thomas Harte
1c5972f7b0 Ensures NTSC raster count rollover; previously it was positing a line '261' for half of '0'. 2018-04-08 16:18:41 -04:00
Thomas Harte
3e846f89a1 Introduces different clipping zones for NTSC and PAL output. 2018-04-05 21:25:19 -04:00
Thomas Harte
60c1da6a66 Causes the 6560 to obey set_sample_volume_range. 
Thereby resolves a clipping issue.
 2018-04-05 21:04:46 -04:00
Thomas Harte
0ee40e8556 Reintroduces 90% crop for VIC output. 2018-03-31 20:57:45 -04:00
Thomas Harte
912791d3d4 Causes the s-video path correctly to function. 2018-03-30 18:24:18 -04:00
Thomas Harte
163a61dd63 Corrects SVideo-as-composite output; the Atari and Vic-20 now both supply svideo. 2018-03-30 13:16:18 -04:00
Thomas Harte
33281b9d89 Introduces S-Video as a video signal type at the interface level. 2018-03-30 10:25:41 -04:00
Thomas Harte
e1aa3e5a7f Imports chrominances from the TED documentation. They seem to apply to the VIC-I also. 2018-03-29 20:04:37 -04:00
Thomas Harte
3b26e0a7c5 Tweaks NTSC colour generation. 2018-03-26 21:22:06 -04:00
Thomas Harte
a776bec46a Tweaks PAL colours for the 6560 to be closer to screenshots found online. 2018-03-26 19:02:16 -04:00
Thomas Harte
a301964bd0 Ensures all audio queues are fully merged before machine destruction. 
Thereby avoids a race condition.
 2018-03-22 21:59:19 -04:00
Thomas Harte
48737a32a7 Introduces formal setting of the output volume to SampleSource. 
Previously every output device was making its own decision. Which is increasingly less sustainable due to the CompoundSource.
 2018-03-09 13:23:18 -05:00
Thomas Harte
705d53cc21 Picks a phase for the TMS empirically. 2018-03-03 13:53:00 -05:00
Thomas Harte
3c5a8d9ff3 Adds Super Game Module support for the ColecoVision. 2018-03-03 13:08:33 -05:00
Thomas Harte
ea13c7dd32 Implements multicolour mode on the TMS. 2018-03-02 23:08:01 -05:00
Thomas Harte
86239469e7 Allows SN76489 consumers to apply an additional divider that reduces computation. 2018-03-01 18:51:05 -05:00
Thomas Harte
7890506b16 Gives the SN76489 its proper dividers and personalities. 2018-02-28 22:36:03 -05:00
Thomas Harte
5b854d51e7 Corrects out-of-bounds access. 2018-02-27 22:45:45 -05:00
Thomas Harte
d4df101ab6 Makes a first attempt at implementing the SN76489. 2018-02-27 22:25:12 -05:00
Thomas Harte
0ad2676640 Adds a class for the SN76489 and wires it into the ColecoVision. 2018-02-26 22:04:34 -05:00
Thomas Harte
cabad6fc05 Optimises the inner TMS loops slightly. 2018-02-21 21:29:17 -05:00
Thomas Harte
2fe0ceb52a Sets TMS input gamma. 2018-01-13 22:19:41 -05:00
Thomas Harte
2f59226300 Fixes: DiskROM drive motor control, track_for_sectors' sides. 2018-01-07 20:02:40 -05:00
Thomas Harte
793ef68206 Implements unconditional force interrupt for the WD. 2018-01-07 19:42:38 -05:00
Thomas Harte
2ffde4c3c2 Corrects SCC volume errors. 
Which were leading to substantial overflow.
 2018-01-07 09:59:00 -05:00
Thomas Harte
57ddfcd645 Corrects AY counter type. 2018-01-06 23:16:01 -05:00
Thomas Harte
fc16e8eb8c Makes first attempt at actually implementing the SCC. 2018-01-06 23:15:42 -05:00
Thomas Harte
655b971976 Establishes that there is such as a thing as a Konami SCC. 
Creates one, ensures it appears in memory when intended to, lets it handle reads and writes. It currently does nothing.
 2018-01-06 20:15:55 -05:00
Thomas Harte
bcc7ad0c30 Corrects bad TMS sprite selections on the top row of the screen. 2018-01-06 16:26:11 -05:00
Thomas Harte
2dc1d4443e Separates LowpassFilter and SampleSource. 2017-12-18 21:39:23 -05:00
Thomas Harte
f8a2459c91 Corrects two lingering adaptation errors in the Vic-20. 2017-12-17 21:43:08 -05:00
Thomas Harte
ac80d10cd8 Separates the component parts of running an audio stream: task deferral, filtering and generation. 
Walking towards improving opportunities for composition.
 2017-12-17 21:26:06 -05:00
Thomas Harte
ec4c259695 Removes unused file. 2017-12-14 21:19:09 -05:00
Thomas Harte
ad50b6b1fb Corrects TMS' get_time_until_interrupt when the next interrupt is exactly a frame away. 2017-12-14 21:12:51 -05:00
Thomas Harte
3da323c657 Corrects lingering free TMS read. 2017-12-14 20:30:56 -05:00
Thomas Harte
aca7842ca4 Better documents and tidies the TMS9918. 2017-12-14 20:27:26 -05:00
Thomas Harte
c36de4f640 Attempts real VRAM access timings, correcting a frame timing error as I go. 2017-12-13 22:37:27 -05:00
Thomas Harte
5d0c33d545 Corrects occasional TMS sprite glitching. 2017-12-12 22:19:33 -05:00
Thomas Harte
b0616ee10c Adds one-before-the-graphics as a line for video collection. 
Thereby corrects sprites on line 0.
 2017-12-12 21:35:33 -05:00
Thomas Harte
798cdba979 8255: update_outputs now affects only those ports designated as outputs. 2017-12-10 17:55:37 -05:00
Thomas Harte
f957344ac4 Corrects TMS failure to show background through tile layer. 2017-12-09 23:15:04 -05:00
Thomas Harte
b3fbd0f352 Tidies up some of the TMS' magic constants. 2017-12-09 23:08:07 -05:00
Thomas Harte
042edc72f7 Adjusts TMS declared timing so as to be in-phase with an NTSC clock, and adopts an alternative palette. 2017-12-09 22:28:34 -05:00
Thomas Harte
943418c434 Reformulates TMS sprite plotting to set the collision flag and to support magnified sprites. 2017-12-09 20:30:12 -05:00
Thomas Harte
7d7e2538bd Introduces a computationally simplified inner loop for TMS graphics modes, modelled on that for text. 2017-12-09 16:02:33 -05:00
Thomas Harte
7a544731e2 Makes minor tidiness improvements to the TMS. 2017-12-08 22:20:21 -05:00
Thomas Harte
e1914b4f16 Attempts to add a proper intermediate buffer for sprites to allow the split of collection and output. 2017-12-08 22:12:39 -05:00
Thomas Harte
8653eb8b55 Corrects various latent errors in optimised TMS video collection. 2017-12-06 20:24:29 -05:00
Thomas Harte
a4f0a260fd Reformulates the TMS graphics mode fetch loop to try to eliminate heavy conditionality. Temporarily introduces some sprite selection issues. 2017-12-05 22:39:03 -05:00
Thomas Harte
d4a53e82bb Replaces manual retread of memcpy with standard memcpy. 2017-12-05 18:21:34 -05:00
Thomas Harte
6eedc99286 Makes substantial optimisations to text mode. 
Character optimisations to come.
 2017-12-04 22:18:51 -05:00
Thomas Harte
a473338abe Makes minor type conversion fixes. 2017-12-03 22:24:48 -05:00
Thomas Harte
ad3df36c20 Corrects sprite information collection to cover all four. 2017-12-03 14:51:55 -05:00
Thomas Harte
38b11893e8 Takes first steps towards sprite display on the TMS. 2017-12-02 22:13:43 -05:00
Thomas Harte
e4534775b0 Cleans up and zooms in on the TMS slightly. 2017-12-02 17:48:31 -05:00
Thomas Harte
fe0cdc8d69 Corrects colour fetching in TMS Graphics II to be a function of row. 2017-12-02 16:10:29 -05:00
Thomas Harte
ca26ce8400 Slightly corrects style errors in the Cartridge hierarchy, and introduces mapping of .ROM to the MSX when appropriate. 2017-12-02 16:01:30 -05:00
Thomas Harte
d3dd8f3f2a Implements screen 2 addressing. 2017-12-02 14:05:52 -05:00
Thomas Harte
3c8d2d579d Resolves remaining sources of text mode instability. 2017-11-30 22:48:07 -05:00
Thomas Harte
edcbb3dfed Tidies code a little and thereby uncovers and corrects one cause of output instability. 2017-11-30 22:19:53 -05:00
Thomas Harte
9c8158753e Makes a first attempt at displaying text mode. 2017-11-30 21:35:26 -05:00
Thomas Harte
ee84f33ab5 Ensures that the 9918 admits that it is the source of interrupts. 2017-11-29 21:33:43 -05:00
Thomas Harte
aa4eef41d8 Seeks to introduce MSX interrupts. 2017-11-29 20:31:55 -05:00
Thomas Harte
ecd7d4731b Advances emulation to showing what looks like appropriate text on screen. 2017-11-28 21:27:15 -05:00
Thomas Harte
563aa051e4 Simplifies code a little and gives something on screen. 2017-11-28 21:19:28 -05:00
Thomas Harte
642bb8333f Introduces something of a first attempt at graphics collection and display. An unsuccessful attempt. 2017-11-28 21:10:30 -05:00
Thomas Harte
c558e86e03 Adds border colour output. 2017-11-27 22:05:40 -05:00
Thomas Harte
dbb14ea2e2 Corrects counting deficiencies that could produce an unstable display. 2017-11-27 21:36:12 -05:00
Thomas Harte
173e16b107 Corrects the 9918 so that it terminates. 2017-11-27 19:48:04 -05:00
Thomas Harte
7d2adad67e Adds the absolute most basic version of in-frame time keeping, to display a white square. 2017-11-27 19:43:33 -05:00
Thomas Harte
d33612def5 Ensures the MSX provides a clock to the VDP. 2017-11-26 20:07:30 -05:00
Thomas Harte
9cb6ca3440 Adds elementary decoding of VDP accesses. 2017-11-26 20:01:11 -05:00
Thomas Harte
0eb5dd9688 Introduces the fundamentals of bus routing for the MSX. 2017-11-26 16:47:59 -05:00
Thomas Harte
a14b53a9ab Adds a TMS9918 skeleton plus enough in the MSX to get to a blank screen in SDL/kiosk mode. 2017-11-26 13:28:26 -05:00
Thomas Harte
c827d14d97 Corrects various GCC warnings across the 6560, CPC, TIA, Oric video and elsewhere. 2017-11-12 17:17:27 -05:00
Thomas Harte
5408efe9b5 Flags obvious default options within the 6560, Vic-20 and DynamicMachine. 2017-11-12 16:41:09 -05:00
Thomas Harte
6d80856f02 Attempts to eliminate warnings around a meaningless value and an unused label in the 8272. 2017-11-12 16:34:51 -05:00
Thomas Harte
4778616fd7 Eliminates unused result and unused label. 2017-11-12 16:30:23 -05:00
Thomas Harte
5aef81cf24 Commutes cross-platform #pragma marks to //MARK:s. 2017-11-12 15:59:11 -05:00
Thomas Harte
2e15fab651 Doubles down on <cX> over <X.h> for C includes, and usage of the namespace for those types and functions. 2017-11-11 15:28:40 -05:00
Thomas Harte
5b6ea35d96 Corrects initialisation ordering for the ZX80/81, C1540 and AY-3-8910. 2017-11-10 22:31:27 -05:00
Thomas Harte
4cbc87a17d Corrects out-of-order initialisations for the 1770, Atari 2600 joystick, Pitfall II bus extender, Microdisc and 6502. 2017-11-10 22:20:44 -05:00
Thomas Harte
ff7ba526fb Corrects improper initialisation order on the 6560. 2017-11-10 22:05:35 -05:00
Thomas Harte
cb015c83e1 Eliminated C99-style struct initialisations. 2017-11-10 19:14:19 -05:00
Thomas Harte
c0055a5a5f Further builds up SConstruct, correcting many missed imports and a couple of improper uses of C99 in C++ code. 2017-11-09 22:04:49 -05:00
Thomas Harte
f95515ae81 Eliminates a large number of instance of end-of-line tabs. 2017-11-07 22:51:06 -05:00
Thomas Harte
ad9df4bb90 Commutes uint8_t *, uint16_t *, uint32_t *, size_t, off_t and long to functional-style casts. 2017-10-21 22:30:15 -04:00
Thomas Harte
ec999446e8 Commutes int and unsigned casts to the functional style. 2017-10-21 21:00:40 -04:00
Thomas Harte
5e3e91373a Switches all unsigned int and double casts to functional style. 2017-10-21 19:49:04 -04:00
Thomas Harte
91b867a7b3 Ensures full 8272 instance state initialisation. 2017-10-17 22:11:01 -04:00
Thomas Harte
3944e734d3 Ensures full 6845 instance state initialisation and uses an unsigned shifter. 2017-10-17 22:10:28 -04:00
Thomas Harte
97a2be71e3 Introduces flush_tracks to Drive, while switching its interface to using Track::Address and adjusting associated integer types. 2017-10-06 21:45:12 -04:00
Thomas Harte
edb9fd301c Begins this project's conversion to functional-style casts. 2017-10-03 22:04:15 -04:00
Thomas Harte
c7f27b2db4 Renames MFM.[c/h]pp as per its new remit: encoding only. 2017-09-24 21:40:43 -04:00
Thomas Harte
2a08bd9ecc Factors shifting plus stateful [M]FM token recognition out of the MFMDiskController. 
Given the proliferation of MFM-related classes, establishes a subdirectory for them.
 2017-09-24 20:07:56 -04:00
Thomas Harte
698e4fe550 Tidies the Disk file hierarchy. 2017-09-22 22:39:23 -04:00
Thomas Harte
d6a5f9a29e Revokes unnecessary change. 2017-09-16 18:24:13 -04:00
Thomas Harte
0d84b4b9dd Removes some redundant end_writing calls. 2017-09-16 17:09:17 -04:00
Thomas Harte
98751e6ac8 Ensures that all result phases are exactly the intended length by replacing accumulation with assignment. 
Also attempts a different version of control mark behaviour. Experiments.
 2017-09-15 22:59:26 -04:00
Thomas Harte
35fe4d50d4 Adds command termination upon drive becoming unready, and copies head and drive selection into ST0. 2017-09-15 20:26:41 -04:00
Thomas Harte
4d4a0cf1d2 Puts the disk controller back into the loop with knowledge about reading mode, and uses that knowledge to cut off the PLL. 2017-09-14 22:30:40 -04:00
Thomas Harte
b62f3e726a Adds a start-of-execution-phase get-out for drives that aren't ready. 2017-09-12 20:43:53 -04:00
Thomas Harte
2f13517f38 Adjusts the 1770 not to talk directly to the drive about motor status. 2017-09-11 22:10:56 -04:00
Thomas Harte
d3c385b471 Separates the 8272's drive selection signalling from actual drive ownership. 
Thereby returns working motor control to the CPC.
 2017-09-11 21:25:26 -04:00
Thomas Harte
96bf133924 Withdraws requirement for DiskController users to specify a PLL multiplier or to provide rotation speed. 
In the latter case because it's no longer of any interest to the controller, and in the former because I'd rather it be picked automatically.
 2017-09-10 22:56:05 -04:00
Thomas Harte
0622187ddf Strips Controller of all capabilities now housed on the Drive. 2017-09-10 19:23:23 -04:00
Thomas Harte
90c7056d12 Started devolving timed event loop logic down to the drives, moving them closer to modelling real life. 2017-09-10 14:43:20 -04:00
Thomas Harte
ff510f3b84 Explicitly disallows copying of VIAs, and marks the constructor as noexcept. 2017-09-05 21:21:23 -04:00
Thomas Harte
7fd6699e0b Corrects comment indentation. 2017-09-05 21:15:15 -04:00
Thomas Harte
450712f39c Improves and corrects 6522 header documentation. 2017-09-04 14:32:34 -04:00
Thomas Harte
24b3faa427 Deconstitutes the 6522 into component parts, templated and non-templated. 
Adjusts the Oric, Vic-20 and C-1540 accordingly, albeit with the quickest possible solutions.
 2017-09-04 14:26:04 -04:00
Thomas Harte
b30bb2a234 Adds an initial implementation of display skew, as a completely live property. 2017-08-29 22:16:40 -04:00
Thomas Harte
334afbc710 Removes const from get_status and get_register, as both may now logically mutate the object. 2017-08-27 18:13:55 -04:00
Thomas Harte
17c13624e5 Improved comments. 2017-08-27 18:11:40 -04:00
Thomas Harte
113349d272 Started making some formal admissions that different CRTC models exist. Plenty yet to do. 2017-08-27 18:10:07 -04:00
Thomas Harte
bdda701207 Reverts previous unevidenced change. 2017-08-26 22:58:16 -04:00
Thomas Harte
487fe83dca Ensures that vertical sync and end-of-visible-lines conditions potentially trigger whenever line_counter_ changes, not only when it increments. 2017-08-26 17:54:54 -04:00
Thomas Harte
6c5a03187b Relocates the HSYNC start test, in order to pass Arnold's cpctest HSYNC start position conformance test. 2017-08-26 17:22:48 -04:00
Thomas Harte
7d7aa2f5d5 Eliminates repetition of the unpacking of register 3 into a horizontal sync count. 2017-08-26 14:37:03 -04:00
Thomas Harte
28550c0227 Breaks the 6845 bus cycle into a phase 1 and a phase 2 per the belief that sync line changes, which are observable, happen at the end of the first phase rather than at the beginning of the next. This may have interrupt timing effects, as machines often derive an interrupt from sync. 2017-08-26 13:56:23 -04:00
Thomas Harte
6e99169348 Permits the 6845's bus state to be examined by an owner, eliminating the need to buffer it in the bus handler. But more than that it allows the CRTC to decide when it adjusts the various outputs respective to the main phase. So a net effect of the change is that the CPC now sees vsync a cycle earlier, because my current reading of the 6845 datasheet is that it is set at the end of phase 1, not the beginning of the next phase 1. 2017-08-26 12:59:59 -04:00
Thomas Harte
3caa4705ca Limits sync counter size. 2017-08-26 12:31:19 -04:00
Thomas Harte
039aed1bd1 Switches the two sync counters to upward-going rather than downward, as a more likely match to the way the rest of the 6845 implementation. 2017-08-25 21:26:01 -04:00
Thomas Harte
a914eadc85 Ensured that register 6 is checked on every loop. 2017-08-22 22:17:45 -04:00
Thomas Harte
e956740c56 Refactors the 6845 more clearly to break out the acts of ending a line and ending a frame, changing the way the memory address is altered — the end-of-line value is provisionally stored and then used if necessary — in order to do so. 2017-08-22 21:54:48 -04:00
Thomas Harte
e88a51e75e Worked logic all the way down to the CPC. If the 8272 announces that it is asleep, it is now no longer clocked. Also very slightly cut down on IRQ line chatter to the Z80. 2017-08-20 12:05:00 -04:00
Thomas Harte
2d9efccc98 Introduced a master 'is sleeping' flag. I'm starting to think there's a pattern forming here. 2017-08-20 10:43:53 -04:00
Thomas Harte
8ce46b6e49 Having spotted that I was using my single-character loop counter names incorrectly (quelle surprise!), got a bit more explicit. Also flattened into a single loop so that I can break rather than returning. 2017-08-20 10:32:09 -04:00
Thomas Harte
669e0caff5 Ensured the head_unload_delay values are properly seeded, and generalised the quick escape. 2017-08-19 22:06:56 -04:00
Thomas Harte
e208f03636 Corrects the US colour palette, effectively undoing what was a mistaken adjustment for the time when Oric-centric phase alignment was built into the CRT based on a false calculation that it wouldn't affect the machines that generate chrominance functionally. 2017-08-16 09:58:34 -04:00
Thomas Harte
cc9d23f23b Inverted meaning of register_masks, as it's a bit weird that the mask is inverted immediately upon usage. It's a left-over from thinking the unused bits should be 1s; unit tests reveal they should be 0s. Comment updated appropriately. 2017-08-16 09:29:48 -04:00
Thomas Harte
1a831bcf9b Quick fix: supply the port being written to correctly. 2017-08-16 09:15:57 -04:00
Thomas Harte
82367a2246 Added documentation. 2017-08-16 09:14:56 -04:00
Thomas Harte
3947347d88 Introduces active input handling for the AY and uses it in the CPC to give proper, active keyboard input, rather than push-on-select, which was only ever a temporary hack. Also maps a few more keys for the Amstrad. 2017-08-15 22:47:17 -04:00
Thomas Harte
aefbafa18d Centralised the 8272's actions of setting the non-DMA execution flag, picking the drive and head and loading the head for accessing commands, and switched error flag if read ID doesn't find anything. 2017-08-15 21:49:10 -04:00
Thomas Harte
d12c834f9c Increased amount reported. 2017-08-15 20:35:33 -04:00
Thomas Harte
56de5cb2b3 Removed one further logging event. 2017-08-15 20:18:32 -04:00
Thomas Harte
709257a0c5 Quick fix: also treat reception of sync as a reason not to stop looking for a data address mark. 2017-08-15 20:16:56 -04:00
Thomas Harte
75a9d2bb33 Started withdrawing logging, reduced index hole count back to the correct number and tried to increase read_data rigour. 2017-08-15 20:12:01 -04:00
Thomas Harte
73080d6c36 Added an easy way for disk controllers to clamp termination of written data exactly to the index hole. 
This commit also temporarily provides a whole load of extra logging and minor logic improvements from the 8272. I'm mid-flow on finding a particularly vicious error in its handling of writing; wait for the pull request. But, at least: now waits for the first part of a post-ID gap before writing data, and attempts partially to handle appearance of the index hole during writing a track. More work to do on that though.
 2017-08-15 16:05:10 -04:00
Thomas Harte
9d77f33611 Dealt with another source of repeating magic constants: the command numbers. 2017-08-15 11:06:10 -04:00
Thomas Harte
7d132f81f7 Increased logging by quite a distance and made an attempt once again to allow the processor some time to supply the first byte when writing before declaring overrun. 2017-08-15 10:50:28 -04:00
Thomas Harte
6553bf05b4 Corrected multi-sector reads: ensured the incremented sector number isn't replaced by the original, and that the controller returns to scanning mode. 2017-08-14 22:27:31 -04:00
Thomas Harte
0816d3f5a9 Corrected 'read deleted data' command. It's 0xc, not 0xb. 2017-08-14 21:41:20 -04:00
Thomas Harte
55055c7847 Minor: ensured immediate line comparison works. But I think my problem might be trying to do this as straight line logic? 2017-08-14 19:08:20 -04:00
Thomas Harte
cddcd0fb79 Put my money where my mouth is and switched the superclass of WD1770 to MFMController, eliminating duplicated (/factored out) code. 2017-08-14 16:32:53 -04:00
Thomas Harte
a366298022 Factored out the standard [M]FM gap and mark groups, to increase 8272 readability and because it's pretty-much certain I'll need them again if ever I try to tackle e.g. the 8271. 2017-08-14 16:03:35 -04:00
Thomas Harte
4df9307d25 Factored out the dull and repetitious stuff of writing n bytes of the same value. 2017-08-14 15:50:36 -04:00
Thomas Harte
9038ba622e Added a quick version of read track. 2017-08-14 14:34:56 -04:00
Thomas Harte
7b8bb0297a Implemented single density version of format track. 2017-08-14 13:03:17 -04:00
Thomas Harte
0da02d3902 Added read/write escape clauses if faced with a read-only disk. 2017-08-14 12:53:18 -04:00
Thomas Harte
2e5ad19fe1 Minor tidying. 2017-08-14 12:42:48 -04:00
Thomas Harte
a10389a22c Factored out the stuff of stuffing the bus. 2017-08-14 12:42:22 -04:00
Thomas Harte
cefec7a19f Sought more robustly (i.e. less repetitively) to handle dispatch, including cancelling seeks where appropriate. 2017-08-14 10:37:39 -04:00
Thomas Harte
7264fbb3d2 read_id now clears status. I probably need to find a way to generalise this. 2017-08-14 09:58:55 -04:00
Thomas Harte
8a7b23dc9e Ensured data-accessing commands cancel seeks on their drives. Also introduced a count of drives currently seeking in order to make for a slightly better broad-phase test in run_for. 2017-08-14 09:45:39 -04:00
Thomas Harte
b7065575f3 Added (empty) call-ins for DMA usage; switched to having the 'is seeking' bit in the status register stay high until sense interrupt status, but now it goes high even for seeks that don't actually go anywhere, and corrected interpretation of the specify command, with a positive result: the received step rate time, now that it's being interpreted correctly, is much shorter. 2017-08-14 09:04:22 -04:00
Thomas Harte
7ea703f150 Started making provisions for a DMA-compatible implementation. Re: the CPC, it sounds like DMA acknowledge might be permanently wired, causing DMA mode seemingly to work from the 8272's point of view. 2017-08-14 08:38:00 -04:00
Thomas Harte
1011143dbe Sought to correct my interpretation of 'gap 3'. 2017-08-13 21:52:48 -04:00
Thomas Harte
9ace6e1f71 Applied minimum constraints for specified parameters. 2017-08-13 19:25:57 -04:00
Thomas Harte
5221837be8 Fixed Non-DMA flag for the format track execution phase. The emulated machine now provides sector details. 2017-08-13 18:51:06 -04:00
Thomas Harte
e1e9a06712 Made an attempt at format a track. 2017-08-13 18:05:19 -04:00
Thomas Harte
b0a7208cc7 Strung together a very basic version of 8272 write [/deleted] data. Lots of cases as-yet unhandled. 2017-08-13 12:50:07 -04:00
Thomas Harte
eec42aa7ae Entrusted further status to drives; also adjusted them to report read only if diskless, which I now believe to be correct. 2017-08-13 11:50:49 -04:00
Thomas Harte
5f42022c1d Added a tester for the control mark. 2017-08-12 17:35:14 -04:00
Thomas Harte
11d0c37506 Attempted to find a more expressive way for maintaining state — macros for all conditions, to bind both values and destinations. 2017-08-12 17:33:52 -04:00
Thomas Harte
27d1dc5c37 Removed some old printfs. 2017-08-12 16:49:20 -04:00
Thomas Harte
7135259cc1 Sought to flesh out error conditions. 2017-08-12 16:36:37 -04:00
Thomas Harte
4909325e79 Implemented read deleted data. 2017-08-12 13:01:17 -04:00
Thomas Harte
a4ee697ed1 Quickie: head unload is scheduled only if the head is presently loaded. 2017-08-12 12:53:45 -04:00
Thomas Harte
0f15a2f97f Relented: it actually looks like status bytes aren't per-drive. But each drive may fail at seeking individually. So that piece of state accumulates at the 8272 drive. 2017-08-12 12:52:36 -04:00
Thomas Harte
89ace671a4 Corrected unload time. Was 8000 times too short. 2017-08-12 09:44:01 -04:00
Thomas Harte
e7db2a2f6d Sought to introduce head loading and unloading delays. 2017-08-12 09:36:21 -04:00
Thomas Harte
ffb1a14ace Minor: clear status registers before a read data. 2017-08-11 18:56:33 -04:00
Thomas Harte
e4f04d0977 Merge branch 'master' into AYFidelity 2017-08-11 14:41:08 -04:00
Thomas Harte
a5593bec79 Threw in support for the light-pen trigger. 2017-08-10 15:00:14 -04:00
Thomas Harte
a1e2646301 Imposed counter size limits. 2017-08-10 14:58:24 -04:00
Thomas Harte
6a6e5ae79c Forced users of the 6845 to be explicit about which type. So far with no effect. 2017-08-10 12:28:57 -04:00
Thomas Harte
02d792c003 Simplified logic slightly, avoiding repetition. 2017-08-10 11:48:37 -04:00
Thomas Harte
be8e7a4144 Eliminated false register aliasing, restricted register sizes and locked out reading and writing where appropriate. 2017-08-10 11:22:30 -04:00
Thomas Harte
b1dbd7833a Merge branch 'master' into 6845Address 2017-08-10 11:15:08 -04:00
Thomas Harte
a4c910f1de This appears to be a more accurate take on 6845 address advancement — it is necessary that character output has finished for the line address to be updated. 2017-08-10 11:12:53 -04:00
Thomas Harte
2eed24e859 Made an initial attempt at [a subset of] multi-sector reads. 2017-08-10 11:11:26 -04:00
Thomas Harte
b11d142cff Switched to descriptive names. 2017-08-08 20:35:41 -04:00
Thomas Harte
021ff8674e Added something for sense drive status. 2017-08-08 20:30:54 -04:00
Thomas Harte
e3d1f4fe1e Subjectively, this might be more correct. It definitely prevents intermediate frequencies. More research required. 2017-08-08 17:58:35 -04:00
Thomas Harte
3bdedfd749 Improved comments. 2017-08-08 07:44:46 -04:00
Thomas Harte
46278ff297 Experimental: is this meant to be a compare-before-increment? 2017-08-07 23:02:29 -04:00
Thomas Harte
390ecec3d9 Added: now declines to pass on output if in input mode for ports A and B. 2017-08-07 19:56:22 -04:00
Thomas Harte
41a30c147d Adjusted: invalid register selection simply deselects all registers. 2017-08-07 19:51:36 -04:00
Thomas Harte
4709ae80cb Added port direction tests. 2017-08-07 19:36:55 -04:00
Thomas Harte
7fbb455836 Per the CPC test I'm checking, 0s should be returned for non-retained bits, not 1s. 2017-08-07 19:07:12 -04:00
Thomas Harte
745afd217f The port input/output flags are now honoured; reading a port that is set as an output returns the current output value. 2017-08-07 19:01:18 -04:00