5713 Commits

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Author	SHA1	Message	Date
Thomas Harte	ac39fd0235	Starts work on the DMA controller.	2019-10-26 21:33:57 -04:00
Thomas Harte	ecc0cea5a1	Added a potential branch for the newer TOS memory map.	2019-10-26 16:52:06 -04:00
Thomas Harte	eae11cbf17	Adds a dummy response for mouse interrogation.	2019-10-26 16:14:24 -04:00
Thomas Harte	e96386f572	Takes another stab at MFP interrupt management.	2019-10-26 15:55:19 -04:00
Thomas Harte	a8d481a764	Writes to the pending register appear to be able to clear interrupts too.	2019-10-25 22:46:30 -04:00
Thomas Harte	2207638287	Adds hsync and vsync interrupts.	2019-10-25 22:42:13 -04:00
Thomas Harte	872897029e	Attempts a complete wiring of 68901 interrupts.	2019-10-25 22:36:01 -04:00
Thomas Harte	51b4b5551d	Actually, I think the 6850 is active low for interrupts.	2019-10-24 22:37:53 -04:00
Thomas Harte	7a2de47f58	Corrects interrupt mask generation.	2019-10-24 22:37:32 -04:00
Thomas Harte	f2f98ed60c	Attempts some part of interrupt decision making.	2019-10-24 22:33:42 -04:00
Thomas Harte	77f14fa638	Starts trying to make sense of interrupts.	2019-10-23 23:09:49 -04:00
Thomas Harte	f09a240e6c	Gives myself more trace details.	2019-10-21 23:20:03 -04:00
Thomas Harte	092a61f93e	Does a better job of having just 512kb.	2019-10-21 23:10:30 -04:00
Thomas Harte	e30ba58e0d	Attempts to wire ACIA interrupt signals into the MFP.	2019-10-21 23:02:30 -04:00
Thomas Harte	7cb82fccc0	Attempts properly to maintain interrupt flag; adds delegate.	2019-10-21 22:40:38 -04:00
Thomas Harte	ed9a5b0430	Adds receipt interrupt.	2019-10-21 21:27:57 -04:00
Thomas Harte	8f59a73425	Corrects incoming data capture.	2019-10-21 20:18:52 -04:00
Thomas Harte	91223b9ec8	Sets default level to high.	2019-10-21 20:18:33 -04:00
Thomas Harte	83f5f0e2ad	Begins trying to receive ACIA data.	2019-10-21 20:10:19 -04:00
Thomas Harte	cf37e9f5de	Remove source control markers.	2019-10-20 23:40:51 -04:00
Thomas Harte	e4f7ead894	Merge branch 'AtariST' of github.com:TomHarte/CLK into AtariST	2019-10-20 23:40:01 -04:00
Thomas Harte	4134463094	The ACIA now receives bits.	2019-10-20 23:34:30 -04:00
Thomas Harte	83d73fb088	The keyboard now responds to a reset on its serial line.	2019-10-20 23:13:44 -04:00
Thomas Harte	75c3e2dacd	Adds basic, incomplete dispatcher for the intelligent keyboard.	2019-10-20 23:07:19 -04:00
Thomas Harte	cf07982a9b	Ensures good serial line and ACIA behaviour. ... Next stop: having the intelligent keyboard react.	2019-10-20 22:10:05 -04:00
Thomas Harte	313aaa8f95	Silences temporarily.	2019-10-20 20:38:56 -04:00
Thomas Harte	2e86dada1d	Ensures updates even when the event queue is empty.	2019-10-20 20:38:56 -04:00
Thomas Harte	696af5c3a6	Starts to transfer serial line decoding logic into the line itself.	2019-10-20 20:38:56 -04:00
Thomas Harte	f08b38d0ae	Silences, temporarily.	2019-10-20 20:38:55 -04:00
Thomas Harte	9a8352282d	Mostly but not quite fixes serial work.	2019-10-20 20:38:55 -04:00
Thomas Harte	3d03cce6b1	Starts working on the GPIP functionality block.	2019-10-20 20:38:55 -04:00
Thomas Harte	34075a7674	Attempts to tie an intelligent keyboard to the other end of its serial line.	2019-10-20 20:38:55 -04:00
Thomas Harte	f79c87659f	Corrects documentation error.	2019-10-20 20:38:55 -04:00
Thomas Harte	c10b64e1c0	Adds a received_data_ register, that presently can never fill.	2019-10-20 20:38:55 -04:00
Thomas Harte	5d5fe52144	Corrects transmission logic — exactly hitting write_data_time_remaining now works properly.	2019-10-20 20:38:55 -04:00
Thomas Harte	d461331fd2	Ensures remaining_delays_ is set properly after [reset/flush]_writing.	2019-10-20 20:38:55 -04:00
Thomas Harte	ff62eb6dce	The ACIA actually has two clocks, though on an ST they're both 500,000 Hz.	2019-10-20 20:38:55 -04:00
Thomas Harte	374439693e	Ensures serial lines know their writer's clock rate.	2019-10-20 20:38:55 -04:00
Thomas Harte	c4ef33b23f	JustInTimeActors can now specify a clock divider.	2019-10-20 20:38:55 -04:00
Thomas Harte	a7ed357569	Attempts to implement transmission interrupts and ClockingHint::Source.	2019-10-20 20:38:55 -04:00
Thomas Harte	4e5b440145	Attempts mostly to implement 6850 output.	2019-10-20 20:38:55 -04:00
Thomas Harte	2bd7be13b5	Decodes the 6850 control register, and starts working on standardised serial ports.	2019-10-20 20:38:55 -04:00
Thomas Harte	4b09d7c41d	Nudges 6850 towards coherence.	2019-10-20 20:38:55 -04:00
Thomas Harte	97d44129cb	Ensures all 16 data lines reach the video.	2019-10-20 20:38:55 -04:00
Thomas Harte	b0f5f7bd37	Attempts to start producing actual video.	2019-10-20 20:38:55 -04:00
Thomas Harte	d1dd6876b5	Adds the option to affix a standard prefix to log messages.	2019-10-20 20:38:55 -04:00
Thomas Harte	a59ec9e818	Provides a token something where DMA should be.	2019-10-20 20:38:55 -04:00
Thomas Harte	4ead905c3c	Adds an empty shell for the ACIA.	2019-10-20 20:38:55 -04:00
Thomas Harte	127bb043e7	Adds enough logic to advance to an ACIA access error.	2019-10-20 20:38:55 -04:00
Thomas Harte	42ebe06474	Makes an attempt at tracking video sequence points.	2019-10-20 20:38:55 -04:00