Thomas Harte
a7cf7d3183
Resolve LOOPNE, LOOPE, etc.
2023-09-19 13:55:19 -04:00
Thomas Harte
9b3199d97b
Reduce failures to 205/324.
2023-09-19 13:45:19 -04:00
Thomas Harte
e5dfc882cb
Agree that JZ/JNZ are clearer (for me) of the synonyms.
2023-09-19 13:38:08 -04:00
Thomas Harte
3582d2c9e3
Start to beef up operand count list.
2023-09-18 16:34:52 -04:00
Thomas Harte
da953fdf0d
Complete 8086 operation list; standardise enum order.
2023-09-18 16:25:04 -04:00
Thomas Harte
710017ada2
Largely resolve the operation-name problem.
2023-09-18 15:57:26 -04:00
Thomas Harte
f8dc5b8ebc
Attempt to get close on index + base addresses.
2023-09-17 17:05:19 -04:00
Thomas Harte
3e09afbb59
Remove errant square bracket.
2023-06-21 11:57:09 -04:00
Thomas Harte
8578dfbf22
Eliminate various other errant spaces.
2023-05-16 16:40:09 -04:00
Thomas Harte
2b56b7be0d
Simplify namespace syntax.
2023-05-10 16:02:18 -05:00
Thomas Harte
1725894fe9
Eliminate redundant CMPSD, CDQ, CWDE.
...
Also removes IBTS for now, as I'm unclear where it should sit in the opcode map.
2022-03-12 12:24:44 -05:00
Thomas Harte
f1c4864016
Eliminate INSD.
2022-03-12 11:37:21 -05:00
Thomas Harte
e6bd265729
Explain which BOUNDs operand is which.
2022-03-11 20:34:28 -05:00
Thomas Harte
c22e8112e7
Expand exposition.
2022-03-11 20:30:56 -05:00
Thomas Harte
44252984c2
Eliminate INT3 special case.
2022-03-11 14:03:46 -05:00
Thomas Harte
4b4f92780e
Shuffle extension word order.
...
The primary objective here is simplifying index calculation, but as per the note it does also potentially open up options with regard to packing in the future.
2022-03-11 13:24:45 -05:00
Thomas Harte
c744a97e3c
Ensure no extensions for default constructed Instruction.
2022-03-11 11:55:26 -05:00
Thomas Harte
572dc40e6b
Allow assignments.
2022-03-11 09:47:23 -05:00
Thomas Harte
641e0c1afc
Resolve default segment question.
2022-03-10 20:27:35 -05:00
Thomas Harte
673ffc50da
Switch to intended compact version of Instruction.
2022-03-10 15:14:50 -05:00
Thomas Harte
6dc9973754
Incorporate length into Instruction.
2022-03-10 07:12:12 -05:00
Thomas Harte
520baa6ec8
Formalise IndirectNoBase and permit a knowledgable caller to avoid conditionals.
2022-03-09 20:19:40 -05:00
Thomas Harte
bbf925a27e
Clarify, unify and correct decoding and encoding of [CALL/RET/JMP][near/far/relative/absolute].
2022-03-09 16:48:06 -05:00
Thomas Harte
ead8b7437e
Remove done TODO.
2022-03-09 15:26:20 -05:00
Thomas Harte
acd9df6745
Fix segment/offset sizes for far calls.
2022-03-09 15:23:43 -05:00
Thomas Harte
de79acc790
Fix RegAddr/AddrRegs and group 2 decoding.
2022-03-09 08:38:34 -05:00
Thomas Harte
21d4838322
Fix current implementation of data_segment.
...
As far as it goes.
2022-03-08 17:08:21 -05:00
Thomas Harte
41a104cc10
Adds special test/control/debug MOVs.
...
This'll do; it's not ideal but avoids bloating up the `Source` enum.
2022-03-07 17:04:05 -05:00
Thomas Harte
35a66c03c2
Add the SETs.
2022-03-07 10:32:34 -05:00
Thomas Harte
1ea9d3faf8
Introduce additional forms of IMUL.
2022-03-07 09:05:22 -05:00
Thomas Harte
8a0902a83b
Adapts existing opcodes for 32-bit parsing.
2022-03-05 13:52:07 -05:00
Thomas Harte
8ee62b4789
Simplify address size semantics.
...
Since it'll no longer be a mode-dependant toggle, but a fully-retained value.
2022-03-01 17:29:26 -05:00
Thomas Harte
2c816db45e
Refactor: (i) to expose effective address calculation; and (ii) to include address size in Instruction.
2022-03-01 09:36:37 -05:00
Thomas Harte
b920507f34
Double down on AddressT, add an assert on memory_mask.
2022-02-28 10:03:58 -05:00
Thomas Harte
9f12c009d6
Correct data size when accessing address registers.
2022-02-27 19:45:03 -05:00
Thomas Harte
27d1df4699
Introduce enough of a DataPointerResolver test to build but fail.
2022-02-27 18:27:58 -05:00
Thomas Harte
0d7a7dc7c9
Introduce DataPointerResolver, to codify the meaning of DataPointer and validate that enough information is present.
2022-02-27 11:25:02 -05:00
Thomas Harte
b8bff0e7f5
Double up eSP, eBP, eSI, eDI and AH, CH, DH, BH enums, as per Intel's encoding.
2022-02-24 05:16:15 -05:00
Thomas Harte
60bf1ef7ea
Rename SourceSIB to DataPointer, extend to allow for an absent base.
2022-02-23 08:28:20 -05:00
Thomas Harte
95976d8b58
Add missing #include.
2022-02-21 16:33:58 -05:00
Thomas Harte
229af0380c
This is normatively called the address size.
2022-02-21 15:52:16 -05:00
Thomas Harte
b968a662d3
Dump notes on intended Instruction layout, add memory size flag.
2022-02-21 15:48:58 -05:00
Thomas Harte
159e869fe6
Justifies the templatisation.
2022-02-21 15:33:08 -05:00
Thomas Harte
76814588b8
Template Instruction on its content size.
2022-02-21 12:36:03 -05:00
Thomas Harte
9e9e160c43
Eliminate Ind[BXPlusSI/etc] in favour of specifying everything via a ScaleIndexBase.
2022-02-21 11:45:46 -05:00
Thomas Harte
546b4edbf1
Ensure ScaleIndexBase can be used constexpr; add note-to-self on indexing table.
2022-02-20 19:22:28 -05:00
Thomas Harte
63d8a88e2f
Switch to holding the SIB as a typed ScaleIndexBase.
...
(and permit copy assignment)
2022-02-20 17:54:53 -05:00
Thomas Harte
75d2d64e7c
Albeit that it requires nuanced shift/roll semantics, eliminates CL constant.
...
Shifts and rolls are already slightly semantically special for being undefined for values greater than 8/16/32 — i.e. in some implementations they don't even use the entirety of CL, just the low five bits. Which makes me feel a little better.
The upside of no ambiguity between eCX size 1 and CL justifies the trade.
2022-02-20 17:52:19 -05:00
Thomas Harte
a5113998e2
Accept that IN and OUT are going to have special semantics, thereby kill ::AX and ::DX.
2022-02-20 17:15:01 -05:00
Thomas Harte
4d2e8cd71d
Adds a presently-unreachable step for SIB consumption.
2022-02-19 18:00:27 -05:00
