1
0
mirror of https://github.com/TomHarte/CLK.git synced 2024-11-23 03:32:32 +00:00
Commit Graph

77 Commits

Author SHA1 Message Date
Thomas Harte
c3b7d24293 It appears that the attention line is also wired to CB2. So the ball is back in the 6522's court. 2016-07-05 19:19:46 -04:00
Thomas Harte
97751a9d86 Took the preliminary steps necessary to wire up a serial port. 2016-07-05 10:55:47 -04:00
Thomas Harte
82b0bc9b58 Discovered that this is another meaningful usage of using. 2016-07-04 19:10:10 -04:00
Thomas Harte
7fa010a463 Attempted to add support for the most basic of control line output, and slightly to optimise the Vic. 2016-07-01 19:01:22 -04:00
Thomas Harte
69d78dfdb3 Removed logging. 2016-06-26 21:36:26 -04:00
Thomas Harte
843d1fdca7 Added some extra logging while trying to determine what's going on; added interrupt clearing for the control lines. 2016-06-26 21:30:06 -04:00
Thomas Harte
c306d705e1 Made a quick first attempt at all-the-way-through tape wiring for the Vic. 2016-06-26 19:43:09 -04:00
Thomas Harte
37ba42a52f Factored out the stuff of playing a tape, started basic sketch of the Vic-related classes. 2016-06-26 19:03:57 -04:00
Thomas Harte
066db59773 Made a hasty attempt to implement CA1 and CB1 input as a potential source of interrupts. 2016-06-26 16:32:27 -04:00
Thomas Harte
d5e50f5ea0 Got a bit more explicit about how ports are identified on the 6522. 2016-06-26 12:30:01 -04:00
Thomas Harte
65413f078c Factored out the 6532, eventually to make it testable. 2016-06-19 18:57:40 -04:00
Thomas Harte
ce2f5515c0 Made some minor documentation improvements, killed 6522.cpp as the 6522 is going to be a template only, attempting to promote good inlining behaviour. 2016-06-19 18:11:37 -04:00
Thomas Harte
f4915c5ad6 Fixed test and added basic implementation of data direction. 2016-06-18 17:17:03 -04:00
Thomas Harte
5d26cd85a3 Wrote test case for what appears to be correct timer behaviour if those were acting in isolation. Ensured implementation matches test case. 2016-06-18 14:30:23 -04:00
Thomas Harte
394902f409 Switched to clocking the 6522 by the half-cycle. Very trivial test now passes. 2016-06-18 13:57:10 -04:00
Thomas Harte
595791cee0 Made the base 6522 class more abstract: you must now opt-in if you want the IRQ line to be sent to a delegate. 2016-06-18 08:51:18 -04:00
Thomas Harte
d1731b1d26 Hacked my 6522 to work. Mistake is in not returning output as input when appropriate — i.e. that I'm ignoring data direction. Also fixed K and L keys. 2016-06-11 13:06:01 -04:00
Thomas Harte
7a241b5ef5 Added just enough hopefully to allow implementation of the keyboard-input VIA. 2016-06-11 11:34:39 -04:00
Thomas Harte
de84758862 This is how flags writes are supposed to work, it seems. 2016-06-11 07:58:32 -04:00
Thomas Harte
1054793fd7 Fixed interrupt enable register. This makes a lot more sense! 2016-06-11 07:57:04 -04:00
Thomas Harte
82a3c4964b Decided to keep the internal copy of the interrupt enable the other way around. Reduced delegate noise. 2016-06-11 07:49:07 -04:00
Thomas Harte
a71259dec3 Gave the 6522 a full and grouped register set. 2016-06-11 07:12:55 -04:00
Thomas Harte
f3b1d7de82 ... and that's a flashing cursor. Keyboard input next! 2016-06-09 22:37:59 -04:00
Thomas Harte
e99055bedb Attempted switching back to a square wave for the composite video and otherwise implementing what's necessary to get to that flashing cursor — the 6560 returns its scan line and the timing bits of the 6522 are appearing. 2016-06-08 22:15:24 -04:00
Thomas Harte
581eace478 Increased logging slightly, ensured all of colour RAM can be read, slightly improved the 2600 pixel decoder. 2016-06-07 22:01:14 -04:00
Thomas Harte
26ab96868a Decided to turn the 6522 into a template, since it's a per-cycle thing with variable behaviour. Added appropriate memory map callouts to hit the two in the Vic. Though they don't yet do anything. 2016-06-07 19:15:18 -04:00
Thomas Harte
6522530e1c Actually, I'm dithering over whether the 6522 should be an ordinary class or a curiously-recurring template. But it'll need a file, definitely. 2016-06-06 21:56:02 -04:00