38 Commits

Author	SHA1	Message	Date
Thomas Harte	088bc14b11	Begin a reformatting of components.	2024-11-29 22:43:54 -05:00
Thomas Harte	093a029b8c	Further reduce printf footprint.	2024-02-15 13:41:35 -05:00
Thomas Harte	a3d37640aa	Switch include guards to #pragma once.	2024-01-16 23:34:46 -05:00
Thomas Harte	3793fbd978	Remove much unused storage; add virtual destructor.	2023-12-27 11:14:08 -05:00
Thomas Harte	2b56b7be0d	Simplify namespace syntax.	2023-05-10 16:02:18 -05:00
Thomas Harte	4fc25fb798	Adds basic shift input.	2021-11-07 05:18:54 -08:00
Thomas Harte	b827b9e33e	Add necessary shift storage.	2021-11-03 19:26:45 -07:00
Thomas Harte	9ecd43238f	Correct 8520 TOD setting and getting.	2021-10-30 12:02:43 -07:00
Thomas Harte	eb157f15f3	Adds index hole interrupt.	2021-10-09 04:08:59 -07:00
Thomas Harte	73e45511dc	Add missing #include.	2021-10-04 05:26:38 -07:00
Thomas Harte	f8380d2d4c	Add 8250 feature of 'count, regardless'.	2021-08-08 22:32:41 -04:00
Thomas Harte	1f9e41e9cb	Ensure TOD isn't firing from power-on.	2021-08-08 18:51:58 -04:00
Thomas Harte	98bd6fc240	Adds a further logging hint.	2021-08-06 23:16:06 -04:00
Thomas Harte	b9f78f5d33	Fix final timer B test.	2021-08-03 22:27:23 -04:00
Thomas Harte	b4ec9d70da	Adds the CNT input.	2021-08-03 22:19:41 -04:00
Thomas Harte	dd91d793d9	Correct typo.	2021-08-03 21:45:44 -04:00
Thomas Harte	8e51e8eb77	Does just a touch of 6526 TOD work.	2021-08-03 21:13:08 -04:00
Thomas Harte	6210605bc7	Transfers full TOD responsibility onto the chip-specific templates.	2021-08-03 19:10:09 -04:00
Thomas Harte	0245b040b0	Splits TOD storage by model. ... TOD storage will probably end up being a full-on class.	2021-08-03 18:50:58 -04:00
Thomas Harte	8795719c18	This counts reloads, most accurately.	2021-08-03 17:12:08 -04:00
Thomas Harte	6bbbf43341	At least attempts to chain correctly.	2021-08-03 17:03:58 -04:00
Thomas Harte	ee6039bfa5	Writes to a timer _during reload_ now have effect. ... Net: one CIA test passed.	2021-08-03 16:57:05 -04:00
Thomas Harte	ef58ce6277	Gets a bit more rigorous about the clocking stage. ... Albeit without advancing relative to the test.	2021-08-02 21:04:00 -04:00
Thomas Harte	38848ca2db	Rationalises reload logic and cuts storage. ... Failure point is now chaining, I think.	2021-08-02 20:14:01 -04:00
Thomas Harte	77c627e822	Ensure that reading the interrupt flags really clears the master bit. ... Also makes some guesses on one-shot and reload timing. Alas the test isn't in itself specific enough to be more systematic here.	2021-08-02 07:47:08 -04:00
Thomas Harte	c640132699	Reinstates clocking.	2021-08-01 21:35:08 -04:00
Thomas Harte	57dd38aef2	Reintroduces reload-on-off, adds interrupt delay.	2021-08-01 21:09:02 -04:00
Thomas Harte	460a6cb6fe	Attempts a more literal implementation.	2021-08-01 18:14:10 -04:00
Thomas Harte	bcb7bb5cce	Improves logging further. ... To investigate the new perpetual loop.	2021-07-26 17:02:30 -04:00
Thomas Harte	fcd6b7b0ea	Takes further aim at the conters. ... I think test cases are needed, probably.	2021-07-24 16:06:49 -04:00
Thomas Harte	ceca32ceb3	Takes a guess at one-shot mode.	2021-07-24 15:53:18 -04:00
Thomas Harte	77a8ddb95c	Edges towards working counters.	2021-07-23 22:43:47 -04:00
Thomas Harte	c733a4dbf8	Beefs up interrupt awareness.	2021-07-23 21:58:52 -04:00
Thomas Harte	d898a43dff	Implements time-of-day counters, provisionally. ... Interrupts to do.	2021-07-23 21:24:07 -04:00
Thomas Harte	6123349b79	Stubs in control registers and disables exit-on-miss. ... I think I may be running up against the limits of stubbing now. Probably time to implement some stuff.	2021-07-22 19:28:01 -04:00
Thomas Harte	56b62a5e49	Adds a dummy interrupt control register.	2021-07-22 16:09:32 -04:00
Thomas Harte	a030d9935e	Adds port input.	2021-07-18 20:25:04 -04:00
Thomas Harte	67d53601d5	Latch and return data direction. ... Albeit with no port-handling effect yet.	2021-07-18 12:23:47 -04:00