15 Commits

Author	SHA1	Message	Date
Thomas Harte	400f54e508	Introduces failing test for bit b, (hl).	2021-04-10 12:04:48 -04:00
Thomas Harte	e0736435f8	Makes assumption that the address bus just holds its value during an internal operation.	2021-04-10 12:00:53 -04:00
Thomas Harte	b09c5538c6	Adds failing test for simple (ii+n) tests.	2021-04-09 21:28:35 -04:00
Thomas Harte	ce3d2913bf	Advances to 9 source table rows tested out of 37.	2021-04-09 20:38:17 -04:00
Thomas Harte	87202a2a27	Add two further tests, add checking of collected data size for all tests.	2021-04-09 18:32:03 -04:00
Thomas Harte	818a4dff25	Corrects ADD HL, dd test. ... Or, at least, likely corrects. The bus cycle breakdown in the Z80 data sheet implies these accesses should come after completion of the refresh cycle, not during its long tail, so I think +1 is correct.	2021-04-08 22:23:15 -04:00
Thomas Harte	9e506c3206	Adds failing ADD hl, dd test.	2021-04-08 22:19:22 -04:00
Thomas Harte	50f53f7d97	Adds INC/DEC rr and LD SP, HL tests.	2021-04-08 22:14:53 -04:00
Thomas Harte	73fbd89c85	Correct opcodes, ability to terminate on a single-cycle contention.	2021-04-08 22:09:33 -04:00
Thomas Harte	f74fa06f2d	Introduces failing test for LD [A/I/R], [A/I/R].	2021-04-08 20:28:55 -04:00
Thomas Harte	ee989ab762	Fills in the rest of the simple two-byte instructions.	2021-04-08 20:13:52 -04:00
Thomas Harte	818655a9b6	Starts on two-bus-cycle instructions, correcting validators.	2021-04-08 20:01:46 -04:00
Thomas Harte	57a7e0834f	Corrects sampling of MREQ.	2021-04-08 19:21:35 -04:00
Thomas Harte	cd787486d2	Tests all of the single-byte, no-access opcodes.	2021-04-07 22:07:52 -04:00
Thomas Harte	67fd6787a6	Builds what I think I need to validate Z80 address, MREQ, IOREQ and RFSH.	2021-04-07 21:57:40 -04:00