Thomas Harte
6df0227ab1
Hacks in a basic effort at dual playfields.
2021-11-16 18:26:27 -05:00
Thomas Harte
47f36f08fb
Switches to a synchronous audio state machine; renames advance -> advance_dma.
...
I can worry about how to just-in-time things once I better understand the hardware in general.
2021-11-13 15:53:41 -05:00
Thomas Harte
f906bab1a5
Provides feedback on interrupt flags, starts on state machine.
2021-11-13 11:05:39 -05:00
Thomas Harte
fffc03c4e4
Propagates time to the audio subsystem.
2021-11-12 15:30:52 -05:00
Thomas Harte
0a94184d6b
Provides a greater wealth of audio data.
2021-11-11 09:24:15 -05:00
Thomas Harte
7be3578497
Adds a target for audio writes.
2021-11-09 07:11:23 -05:00
Thomas Harte
31e22e4cfb
Provides full serial input.
2021-11-07 05:19:16 -08:00
Thomas Harte
c0c2b5e3a9
Post key actions to the nominated serial line.
...
Albeit that I'm still thinking through whether I want the option of including a clock on Serial::Line. It'd be natural in one sense — there's already one built in — but might weaken Serial::Line's claim to be a one-stop shop for both enqueued and real-time connections without a reasonable bit of extra work.
2021-11-06 12:03:09 -07:00
Thomas Harte
c9bf2dda16
Attempt implementation of disk sync.
2021-11-02 18:18:59 -07:00
Thomas Harte
3ceb378b9b
Relocate disk logic into a separate compilation unit.
2021-11-02 17:35:23 -07:00
Thomas Harte
1cf1c90511
Adds support for interlaced output.
2021-11-02 14:34:03 -07:00
Thomas Harte
d989825216
Add bonus notes on VPOSR.
2021-11-02 03:47:39 -07:00
Thomas Harte
3976420b88
Retains a little more of output controls.
2021-11-01 17:15:36 -07:00
Thomas Harte
2f1ce5fe43
Switch to using the swizzled palette for playfield output.
2021-11-01 14:44:30 -07:00
Thomas Harte
42145a5b8a
Delay bitplane installation until end of slot.
2021-11-01 14:18:58 -07:00
Thomas Harte
4e66017205
Enable sprite reuse and toggle to inactive when visible region is over.
2021-10-31 16:52:48 -07:00
Thomas Harte
4c1ab6ff25
Rethinks bitplane stops.
2021-10-31 09:01:38 -07:00
Thomas Harte
02c88e6826
VHPOSR's fields are the other way around.
2021-10-30 12:04:46 -07:00
Thomas Harte
d25804f4a2
Throws in official register names.
2021-10-29 14:05:11 -07:00
Thomas Harte
edb75e69cb
Implement bitplane modulos.
2021-10-29 11:29:22 -07:00
Thomas Harte
b952d73e83
Disallow programmatic setting of blitter status.
2021-10-29 06:19:57 -07:00
Thomas Harte
da1a69be27
Caps mouse speed.
...
Also takes another guess at CIA interrupt bits. To no avail.
2021-10-27 18:38:02 -07:00
Thomas Harte
139d35c6f9
Switches to basic use of sprite shifters.
2021-10-25 20:58:48 -07:00
Thomas Harte
cb24457b4a
Starts on a two-at-a-time sprite shifter.
2021-10-25 16:30:30 -07:00
Thomas Harte
9f3efb7f05
Limits graphical output to [all but one bit] of the display window.
2021-10-25 14:12:23 -07:00
Thomas Harte
e6001e0f22
Shifts bitplanes irrespective of output window.
2021-10-25 13:59:39 -07:00
Thomas Harte
c6535bf035
Switches bitplane shifter to returning four high-res pixels at a time.
2021-10-25 13:34:36 -07:00
Thomas Harte
7118a515e0
Reduce logging in trustworthy areas.
2021-10-23 20:36:41 -07:00
Thomas Harte
952451c9b8
Add mouse input.
2021-10-23 20:17:13 -07:00
Thomas Harte
610327a04e
Fix sprite H start bit order.
2021-10-22 23:20:20 -07:00
Thomas Harte
2121e32409
Fix sprite bit ordering.
2021-10-22 21:10:01 -07:00
Thomas Harte
7ec21edc2f
Attempts to hack in some form of sprite display.
2021-10-22 19:51:10 -07:00
Thomas Harte
003162f710
Limit to specific purpose.
2021-10-22 16:16:19 -07:00
Thomas Harte
040ac93042
Takes a shot at the vertical stuff of sprite DMA.
2021-10-22 14:32:59 -07:00
Thomas Harte
b489ba3d0d
Adds sprite DMA windows.
2021-10-22 13:07:20 -07:00
Thomas Harte
c5e8b547af
Captures the attach flag and observes activation rule.
2021-10-22 11:21:58 -07:00
Thomas Harte
e67de90ad0
Starts to bring sprites inside DMADevice orthodoxy.
2021-10-21 21:57:46 -07:00
Thomas Harte
c3c84c88a1
Switch to ahead-of-time planar to chunky conversion.
2021-10-21 20:48:57 -07:00
Thomas Harte
0dc9c4cee1
Undo hard-coding of fetch window.
2021-10-19 15:18:39 -07:00
Thomas Harte
b312a61a81
Add two dummy reads.
2021-10-16 13:30:45 -07:00
Thomas Harte
e27a10bde4
Simplify control flow.
2021-10-14 16:47:18 -07:00
Thomas Harte
253a199f27
Fire sync-match interrupt upon any match.
2021-10-14 16:36:17 -07:00
Thomas Harte
b12c640807
Makes drives non-copyable.
...
To avoid error in the future.
2021-10-14 12:37:55 -07:00
Thomas Harte
9be23ecc34
Add end-of-Blit interrupt.
...
Along with a slightly easier path for posting interrupts, in C++ compilation unit terms.
2021-10-13 15:09:19 -07:00
Thomas Harte
eec068914e
Slightly improve logging.
2021-10-11 18:05:57 -07:00
Thomas Harte
39b8285ba5
Trust the HRM on step bit, but catch rising edge.
2021-10-11 07:42:42 -07:00
Thomas Harte
7733fef3bd
DSKLEN has to be written twice.
2021-10-11 06:16:01 -07:00
Thomas Harte
6acddfdb98
Add the sync match interrupt.
...
Albeit that it doesn't yet unblock disk DMA.
2021-10-11 03:37:56 -07:00
Thomas Harte
99492c2ec2
Further tweak logging.
2021-10-10 18:19:50 -07:00
Thomas Harte
846b505d27
Reduce logging; disk data probably isn't the immediate obstacle.
2021-10-10 13:04:10 -07:00
Thomas Harte
8d43b4a98d
Expands Disk DMA access window.
2021-10-10 11:47:02 -07:00
Thomas Harte
9336ffe216
Take a stab at index-hole sync.
2021-10-09 08:01:02 -07:00
Thomas Harte
eb157f15f3
Adds index hole interrupt.
2021-10-09 04:08:59 -07:00
Thomas Harte
d6e2a3f425
Make a first attempt to spool into RAM.
2021-10-08 18:11:47 -07:00
Thomas Harte
b47ca13ed3
Push disk data onwards.
2021-10-08 17:18:11 -07:00
Thomas Harte
67546c4d6e
Per the HRM, the index hole is connected to CIA B, potentially to raise an interrupt.
2021-10-08 17:12:37 -07:00
Thomas Harte
f72deb0a5c
Correct RDY position.
2021-10-08 04:32:13 -07:00
Thomas Harte
616ccbb878
Correct ID bit placement, multiplex with motor state.
...
The latter per my reading of http://www.primrosebank.net/computers/amiga/upgrades/amiga_upgrades_storage_fdis.htm
2021-10-08 04:05:57 -07:00
Thomas Harte
5899af0038
Starts accumulating disk data.
2021-10-07 05:11:32 -07:00
Thomas Harte
33ff4f3b5c
Eliminate drive copies.
2021-10-06 13:40:28 -07:00
Thomas Harte
20bad38d42
Add drive activity lights.
2021-10-06 04:54:40 -07:00
Thomas Harte
92a07398cd
I think CHNG works the other way around.
2021-10-06 04:47:52 -07:00
Thomas Harte
e961d0b4a3
Switch RDY type.
2021-10-06 04:41:09 -07:00
Thomas Harte
2253ff656a
Adds route for inserting disks.
2021-10-05 16:12:30 -07:00
Thomas Harte
18631399ad
Attempts to clock the disk controller.
2021-10-05 15:38:56 -07:00
Thomas Harte
ad4afcdcd5
Switch stepping direction.
...
Empirically, based on the actions of Kickstart, and assuming my confusion is because the relevant signal is active low.
2021-10-05 15:23:48 -07:00
Thomas Harte
2cf5bcc5db
Clarify logic somewhat.
2021-10-05 15:20:05 -07:00
Thomas Harte
1180ad7662
Disables a couple of now-trustworthy LOGs.
2021-10-05 06:51:47 -07:00
Thomas Harte
5463cd1ae3
Attempts to support stepping and head selection.
2021-10-05 06:36:17 -07:00
Thomas Harte
647ec770ce
Implements motor latching, drive ID shift registers.
2021-10-05 05:12:01 -07:00
Thomas Harte
e47bec2e65
Switch CIA B ports over.
2021-10-05 03:38:11 -07:00
Thomas Harte
674941abdf
Starts to add a disk controller.
2021-10-04 16:45:05 -07:00
Thomas Harte
b3f0ca39ed
Adds some unused drives.
2021-10-04 08:12:13 -07:00
Thomas Harte
5ccb512883
Moves the CIAs into the Chipset class.
...
This reflects the routing of interrupt signals for now, but also prepares for the addition of disk drives.
2021-10-04 06:44:54 -07:00
Thomas Harte
0b9ebafc0f
Flip bit deserialisation order.
2021-09-28 22:12:13 -04:00
Thomas Harte
ffcd2ea10c
Attempts more properly to implement line mode.
2021-09-28 21:39:09 -04:00
Thomas Harte
c4ab2bbeed
Hard-code fetch window width. For now.
2021-09-23 22:06:13 -04:00
Thomas Harte
f1d514470d
Add note to future self.
2021-09-23 20:29:39 -04:00
Thomas Harte
60bad22a91
Correct fetch window.
2021-09-23 18:13:24 -04:00
Thomas Harte
e15f1103a0
Takes a shot at low resolution shifting.
2021-09-20 19:00:52 -04:00
Thomas Harte
a4263b5a8c
Ties bitplane collection to line position.
...
Outgoing bug: incrementing the video relative offset too often, due to cycles that are discovered to be CPU-targetted.
2021-09-19 21:55:45 -04:00
Thomas Harte
245b7baa61
Moves the Copper into its own file.
2021-09-16 21:17:23 -04:00
Thomas Harte
0eeaaa150a
Correct Copper start address.
2021-09-16 21:01:37 -04:00
Thomas Harte
692d87f446
Attempts to restrict blitter slot allocation.
2021-09-16 19:56:28 -04:00
Thomas Harte
6572efe2a7
Clarifies word addressing.
2021-09-16 08:24:52 -04:00
Thomas Harte
8aac2bd029
Stubs in serial port status.
2021-09-14 21:53:07 -04:00
Thomas Harte
add11db369
Factors out DMADevice, which is now a parent of Blitter.
2021-09-14 20:51:32 -04:00
Thomas Harte
fd70f7ad43
Attempts to make pixel content observeable.
2021-09-08 20:57:26 -04:00
Thomas Harte
6e034c9b7f
At least manages to place a pixel region on screen.
...
Albeit that I've suddenly realised that I've failed properly to think about high-res versus low-res.
2021-08-11 20:31:37 -04:00
Thomas Harte
52e375a985
Move towards playfield decoding.
2021-08-11 18:47:35 -04:00
Thomas Harte
10a5e7313f
Makes a buggy first attempt at bitplane data collection.
2021-08-10 21:28:48 -04:00
Thomas Harte
ec9cb21fae
Starts towards bitplane collection.
2021-08-10 19:01:41 -04:00
Thomas Harte
fdd02ad6a6
Neaten, slightly.
2021-08-10 09:20:34 -04:00
Thomas Harte
76e9fcc94a
Obey blitter DMA-enable mask.
2021-08-10 09:19:15 -04:00
Thomas Harte
e412927415
Logs a bit more from the Blitter, gives it access to slots.
2021-08-10 07:17:01 -04:00
Thomas Harte
dda154c7c6
Adds nonsense disk reads, which seems to lead to bitplane and blitter requests.
...
Progress, at last!
2021-08-09 20:31:14 -04:00
Thomas Harte
9215535bee
Adds a container for the disk controller.
...
Thereby appears to prove that my Amiga is getting as far as attempting to load from floppy.
2021-08-09 17:35:09 -04:00
Thomas Harte
1502c4530e
Takes a further step towards real timing.
2021-08-08 21:52:28 -04:00
Thomas Harte
db3c158215
Further increases logging.
2021-08-05 20:07:14 -04:00
Thomas Harte
1bae4973bc
Post the serial control write onwards.
2021-07-30 18:24:27 -04:00
