Thomas Harte
a5f9869769
Merge pull request #230 from TomHarte/CyclicShutdown
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Eliminates potential cyclic entry into CSMachine during its `-dealloc`.
2017-08-31 21:23:15 -04:00
Thomas Harte
f10be2a18a
Eliminates potential cyclic entry into CSMachine during its -dealloc.
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Explicit cause: dealloc calls close_output(). That may decide to flush work, indiscriminately. Some of the flushed work might be audio generation. Audio generation might cause the audio queue to react with an out-of-data announcement. Which would cause a fresh attempt to update the CSMachine.
2017-08-31 21:22:23 -04:00
Thomas Harte
c88d627b4e
Merge pull request #229 from TomHarte/Skew
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Adds an initial implementation of display skew to the 6845
2017-08-29 22:32:26 -04:00
Thomas Harte
b30bb2a234
Adds an initial implementation of display skew, as a completely live property.
2017-08-29 22:16:40 -04:00
Thomas Harte
d498080eb4
Merge pull request #228 from TomHarte/CRTCStatus
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Takes initial steps towards supporting CRTC manufacturer diversity.
2017-08-27 22:26:40 -04:00
Thomas Harte
334afbc710
Removes const from get_status and get_register, as both may now logically mutate the object.
2017-08-27 18:13:55 -04:00
Thomas Harte
17c13624e5
Improved comments.
2017-08-27 18:11:40 -04:00
Thomas Harte
113349d272
Started making some formal admissions that different CRTC models exist. Plenty yet to do.
2017-08-27 18:10:07 -04:00
Thomas Harte
0ced7866fc
Merge pull request #227 from TomHarte/NoCPCOptions
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Removes the CPC options panel.
2017-08-27 17:12:24 -04:00
Thomas Harte
d06031dfcb
Removes the options panel for CPC display.
2017-08-27 17:11:35 -04:00
Thomas Harte
3f22a71276
Merge pull request #226 from TomHarte/TargetAwareness
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Substantially rewires Mac-side target selection and as proof-of-concept adapts the generic-side ZX80 to instantiate without wait line support
2017-08-27 16:55:01 -04:00
Thomas Harte
53a88a7e12
Causes the ZX80/81 to omit support for the wait line if being configured as a ZX80.
2017-08-27 16:45:36 -04:00
Thomas Harte
4a66dd9e82
Arranges for the ZX80/81 to get a peek at target configuration prior to construction. I'm as yet undecided on whether to make this the norm.
2017-08-27 16:42:16 -04:00
Thomas Harte
522839143f
Revokes -[CSMachine init] and the slightly troubling create-on-demand semantics it places upon subclasses via .machine. Therefore each machine must announce its own implementation of -init.
2017-08-27 16:36:21 -04:00
Thomas Harte
b4c532c0d5
Merge pull request #225 from TomHarte/TargetHints
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Factors the concept of a target platform out from the static analyser, allowing file formats to opine
2017-08-27 15:46:55 -04:00
Thomas Harte
a3e2d142e3
Extends UEF support to include chunk 0005, the target platform description, which is exposed via TargetPlatform::TypeDistinguisher.
2017-08-27 15:43:09 -04:00
Thomas Harte
63ee8c9d58
Uses file containers' type distinguishers where available, and supplies potential insight to the ZX80/81 analyser as now required.
2017-08-27 15:20:58 -04:00
Thomas Harte
437023bff6
Expands to take an already-accrued list of potential platforms, as that may indicate that one or the other of the ZX80 and ZX81 is already out of contention and therefore save the need to attempt analysis.
2017-08-27 15:20:22 -04:00
Thomas Harte
4465098157
Since it has descendants, gives Storage::Cartridge a virtual destructor.
2017-08-27 15:19:30 -04:00
Thomas Harte
56dd677e9c
Creates a virtual interface that can be adopted by classes that are able to provide some insight as to target machine.
2017-08-27 15:19:03 -04:00
Thomas Harte
9aa150c338
Abstracts the target platform type out from the static analyser's ownership.
2017-08-27 15:02:13 -04:00
Thomas Harte
fab6908129
Corrects the all-RAM Z80 to declare that it needs the wait line to be implemented.
2017-08-26 23:18:11 -04:00
Thomas Harte
e34d4ce903
Merge pull request #224 from TomHarte/OptionalWait
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Makes the Z80's support for WAIT input optional
2017-08-26 23:16:22 -04:00
Thomas Harte
d411827733
Merge branch 'master' into OptionalWait
2017-08-26 23:11:23 -04:00
Thomas Harte
f1ba7755dd
Merge pull request #223 from TomHarte/cpctest
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Moves test for 6845 horizontal sync timing into the time after phase 1 and before phase 2
2017-08-26 23:11:03 -04:00
Thomas Harte
57bfec285f
Makes it optional whether the Z80 supports the wait line. If the wait line isn't in use, runtime costs are decreased because the optional wait cycles need not be iterated over.
2017-08-26 23:08:57 -04:00
Thomas Harte
bdda701207
Reverts previous unevidenced change.
2017-08-26 22:58:16 -04:00
Thomas Harte
487fe83dca
Ensures that vertical sync and end-of-visible-lines conditions potentially trigger whenever line_counter_ changes, not only when it increments.
2017-08-26 17:54:54 -04:00
Thomas Harte
6c5a03187b
Relocates the HSYNC start test, in order to pass Arnold's cpctest HSYNC start position conformance test.
2017-08-26 17:22:48 -04:00
Thomas Harte
97f57a3948
Merge pull request #222 from TomHarte/6845GetState
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Refines observable 6845 behaviour
2017-08-26 14:46:29 -04:00
Thomas Harte
7d7aa2f5d5
Eliminates repetition of the unpacking of register 3 into a horizontal sync count.
2017-08-26 14:37:03 -04:00
Thomas Harte
e7ad79c79a
Breaks apart the CPC's 6845 bus handler to obey phase 1 and phase 2, and now back-dates interrupts when appropriate.
2017-08-26 14:07:51 -04:00
Thomas Harte
28550c0227
Breaks the 6845 bus cycle into a phase 1 and a phase 2 per the belief that sync line changes, which are observable, happen at the end of the first phase rather than at the beginning of the next. This may have interrupt timing effects, as machines often derive an interrupt from sync.
2017-08-26 13:56:23 -04:00
Thomas Harte
6e99169348
Permits the 6845's bus state to be examined by an owner, eliminating the need to buffer it in the bus handler. But more than that it allows the CRTC to decide when it adjusts the various outputs respective to the main phase. So a net effect of the change is that the CPC now sees vsync a cycle earlier, because my current reading of the 6845 datasheet is that it is set at the end of phase 1, not the beginning of the next phase 1.
2017-08-26 12:59:59 -04:00
Thomas Harte
1017bb9f6b
Merge pull request #221 from TomHarte/6845UpCount
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Regularises the 6845 sync counters
2017-08-26 12:51:39 -04:00
Thomas Harte
3caa4705ca
Limits sync counter size.
2017-08-26 12:31:19 -04:00
Thomas Harte
039aed1bd1
Switches the two sync counters to upward-going rather than downward, as a more likely match to the way the rest of the 6845 implementation.
2017-08-25 21:26:01 -04:00
Thomas Harte
d77d7fdd78
Merge pull request #220 from TomHarte/Analysis
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Resolves all current analyser warnings.
2017-08-24 22:19:51 -04:00
Thomas Harte
c6e6c3fcfb
Resolves all current analyser warnings.
2017-08-24 22:18:44 -04:00
Thomas Harte
ecd3350a6f
Merge pull request #219 from TomHarte/ConstSafety
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Makes all of PartialMachineCycle const
2017-08-24 22:04:06 -04:00
Thomas Harte
fa19e2d9c2
Removes some detritus.
2017-08-24 22:00:21 -04:00
Thomas Harte
95d360251d
Makes all of PartialMachineCycle const, with the exception of the target of *value, since that's intended to be writeable by recipients.
2017-08-24 21:32:33 -04:00
Thomas Harte
7af3de010e
Suspected my mode 1 interrupt timing might be off. Reminded myself of the sources. Persuaded myself that it wasn't. Added appropriate comments.
2017-08-23 22:25:31 -04:00
Thomas Harte
cefd421992
Merge pull request #218 from TomHarte/6845Factored
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Refactors the 6845 to make end-of-line and end-of-frame conditions more explicit and to reduce repetition
2017-08-22 22:21:17 -04:00
Thomas Harte
a914eadc85
Ensured that register 6 is checked on every loop.
2017-08-22 22:17:45 -04:00
Thomas Harte
131b340d75
Dodges a lambda copy.
2017-08-22 21:55:10 -04:00
Thomas Harte
e956740c56
Refactors the 6845 more clearly to break out the acts of ending a line and ending a frame, changing the way the memory address is altered — the end-of-line value is provisionally stored and then used if necessary — in order to do so.
2017-08-22 21:54:48 -04:00
Thomas Harte
8afd83b91f
Merge pull request #217 from TomHarte/CompiletimeOptions
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Introduces compile-time selection of minor CPU core features and applies forceinline when appropriate
2017-08-21 22:29:24 -04:00
Thomas Harte
40d7a603db
Ensured that forceinline does nothing in debug builds.
2017-08-21 22:04:15 -04:00
Thomas Harte
ee71be0e7e
Added the option not to include ready line support in the 6502 core, and took advantage of it in the Electron, Oric and Vic-20 implementations. Also tagged those as forceinline and/or override final where applicable.
2017-08-21 21:56:42 -04:00
