Thomas Harte
8578dfbf22
Eliminate various other errant spaces.
2023-05-16 16:40:09 -04:00
Thomas Harte
d9d20d9d30
Walk back slightly.
2021-10-14 18:02:58 -07:00
Thomas Harte
689bfbbdb3
Be overt in initialiser list.
2021-10-14 16:57:26 -07:00
Thomas Harte
c8699d9770
Correct Disk II sleeping test to allow for spin-down.
2021-07-16 17:12:57 -04:00
Thomas Harte
dfe4e49110
Ensure proper in-memory ordering of the b72a2c70 ROM.
2020-12-29 22:08:48 -05:00
Thomas Harte
8aeebdbc99
Remove redundant comment.
2020-07-16 23:26:45 -04:00
Thomas Harte
267006782f
Starts to add Qt target; resolves many build warnings.
2020-05-30 00:37:06 -04:00
Thomas Harte
25996ce180
Further doubles down on construction syntax for type conversions.
2020-05-09 23:00:39 -04:00
Thomas Harte
31c6faf3c8
Adds a bunch of consts.
2020-05-09 21:23:52 -04:00
Thomas Harte
1c154131f9
Expands size of storage in Cycles/HalfCycles; adjusts widely to compensate.
2019-10-29 22:36:29 -04:00
Thomas Harte
c4ab0bb867
Starts sketching out an interface for IWM drives, eliminating a dangling use of unsigned as it goes.
2019-07-10 16:05:59 -04:00
Thomas Harte
b9c2c42bc0
Switches drives to using floats for time counting.
...
Hopefully to eliminate a lot of unnecessary `Time` work; inaccuracies should still be within tolerable range.
2019-07-02 15:43:03 -04:00
Thomas Harte
70c4d6b9b3
Adds a one second delay between controller and drive motor off.
2018-08-03 21:13:18 -04:00
Thomas Harte
98bb5bd9f1
Ensures flux bits are observable for two cycles rather than one; it should be 1us.
2018-07-31 23:01:11 -04:00
Thomas Harte
dde9b73a22
Creates the through-path that will be necessary for RWTS acceleration.
2018-06-09 12:51:53 -04:00
Thomas Harte
076fa55651
Corrects: flux set is no-flux incoming.
...
This restores good sleeping behaviour.
2018-06-03 08:11:17 -04:00
Thomas Harte
75f9e3caeb
Resolves incorrect bracketing.
2018-05-28 17:48:35 -04:00
Thomas Harte
928aab13dc
Introduces more granular clocking announcements to the Disk II.
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As well as making it accept the clock rate it'll actually receive, to supply to the drives, so that they spin at the proper speed.
2018-05-28 17:19:29 -04:00
Thomas Harte
db8d8d8404
Commutes Sleeper to ClockingHint::Source, making state more granular.
2018-05-27 23:17:06 -04:00
Thomas Harte
086b801c29
Mildly rearranges to avoid unnecessary call.
2018-05-22 21:50:07 -04:00
Thomas Harte
e482929da8
Enhances the Disk II's ability to sleep.
...
Also enables Disk II sleep observation in the Oric.
2018-05-19 23:15:28 -04:00
Thomas Harte
ed06533e60
Implements write support out of the Disk II.
2018-05-18 22:07:58 -04:00
Thomas Harte
7b7beb13a3
Eliminates the fiction of setting and getting registers.
...
The Disk II seems lower level than that; it will read the data bus whenever it likes, it is the programmer's responsibility to keep up with that. It also reserves the right not to load the bus regardless of whether it receives a read or write access.
2018-05-17 21:39:11 -04:00
Thomas Harte
c46007332a
Switches to returning the shift register contents on every even read.
2018-05-17 20:18:34 -04:00
Thomas Harte
908d3b0ee5
Slightly wrong as to the details, but gets the controller trying to output.
...
At an initial look, I think the shift register should end up on the data bus for all odd accesses. Need to investigate more thoroughly.
2018-05-16 22:37:22 -04:00
Thomas Harte
8a031b1137
Eliminates 'data' register as it doesn't exist; rejigs state machine command set.
2018-05-16 22:09:59 -04:00
Thomas Harte
1aba9f807e
Ensures proper upward propagation of sleeping from first start.
2018-05-16 22:07:54 -04:00
Thomas Harte
4c49963988
Switches to proper handling of the motor control and write protection.
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Per Understanding the Apple II the drive looks write protected while phase 1 is enabled.
2018-05-16 21:44:09 -04:00
Thomas Harte
0b771ce61a
Removes all instances of the copyright symbol.
2018-05-13 15:19:52 -04:00
Thomas Harte
d703328114
Adds missing #include for memcpy.
2018-05-12 17:54:13 -04:00
Thomas Harte
a43ca0db35
Makes the Apple II an activity source.
2018-05-10 22:17:13 -04:00
Thomas Harte
c3144382c5
Shuffles the Disk II ROM at load time into B.A.P. form.
...
Only if required. In order to support various potential forms of supplied ROM.
2018-05-09 22:03:59 -04:00
Thomas Harte
c3a2f7717b
Makes attempt to implement support for the Pravetz 8D + 8DOS.
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i.e. the Disk II wired up to the Oric, with some ROM swaps.
2018-05-08 22:05:43 -04:00
Thomas Harte
f65c65569a
Makes disk head position explicitly something with sub-integral precision.
...
Also as a drive-by fix, corrects accidental assumption of 10 sectors for all MFMSectorDump descendants.
2018-05-06 23:17:36 -04:00
Thomas Harte
aacf26f05d
Removed logged comment.
2018-04-30 22:03:09 -04:00
Thomas Harte
10c0e687f5
Attempts to introduce sleeping for the Disk II.
2018-04-29 17:51:10 -04:00
Thomas Harte
41075356e2
Makes a first attempt at NIB support.
2018-04-26 22:49:07 -04:00
Thomas Harte
d59db504a3
Adjusted stepper logic; some disks load now.
2018-04-25 21:59:18 -04:00
Thomas Harte
4c6dc597f4
Converts Time::get into a template, introduces a via-a-double fallback for the timed event loop.
2018-04-25 19:54:39 -04:00
Thomas Harte
7061537ff5
Makes joined-up attempt to run data through the Disk II.
2018-04-24 19:44:45 -07:00
Thomas Harte
99de8f1c5c
Inverts the pulse strobe.
2018-04-24 09:03:03 -07:00
Thomas Harte
af61bbc3e2
Attempts actual performance of the state machine.
2018-04-24 08:29:05 -07:00
Thomas Harte
56d88f23ef
Teeters closer and closer to trying actually to run the Disk II state machine.
2018-04-23 22:29:36 -07:00
Thomas Harte
4bff44377a
Attempts to route Disk II requests to the thing itself.
2018-04-23 22:11:31 -07:00
Thomas Harte
72bc5f8d7b
Adds a class to contain the Disk II and begins Apple GCR conversion routines.
2018-04-21 14:33:42 -07:00
