6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2024-11-23 03:32:32 +00:00
Code Issues Projects Releases Wiki Activity
4,579 Commits 8 Branches 121 Tags 496 MiB
bb04981280
Commit Graph

367 Commits

Author SHA1 Message Date
Thomas Harte
bb04981280 I'm still dithering on address management, but this seeks fully to implement ABCD and SUBD bus programs. 2019-03-13 21:08:13 -04:00
Thomas Harte
57898ed6dd This is where my thinking now resides. Two levels of indirection, and consolidated collections. 2019-03-12 22:46:31 -04:00
Thomas Harte
33b53e7605 Settles upon disassembly as the route in, and begins work in that direction. 2019-03-11 22:47:58 -04:00
Thomas Harte
89c71f9119 Introduces EmuTOS, and starts constructing test cases around it. 2019-03-10 18:40:12 -04:00
Thomas Harte
98aa597510 A theoretical 68000 could now perform its /RESET. That's all though. 2019-03-10 17:42:13 -04:00
Thomas Harte
de56d48b2f Embraces a more communicative 68000 bus. 2019-03-10 17:27:34 -04:00
Thomas Harte
4aeb9a7c56 Genericises RegisterPair. 2019-03-09 21:16:11 -05:00
Thomas Harte
b9b52b7c8b Begins some very early sketching out of a 68000. 2019-03-09 00:00:23 -05:00
Thomas Harte
d97348dd38 Eliminates dangling uses of printf. 2019-03-02 18:07:05 -05:00
Thomas Harte
ee89be6730 Removes many stray spaces. 2018-11-23 22:32:32 -05:00
Thomas Harte
364859467f Corrects Rockwell and WDC references. 
Also shuffles the NES CPU type up into the top position, so this is a strict progression in terms of functionality.
 2018-09-27 22:36:45 -04:00
Thomas Harte
8787d85e64 Eliminates #undefs as being (i) unnecessary, now this is a source file; and (ii) incomplete in any case. 2018-08-17 22:24:42 -04:00
Thomas Harte
0e7f54f375 Implements STP and WAI, and ensures all unimplemented 65C02 instructions are NOP for all 65C02s. 2018-08-17 21:49:06 -04:00
Thomas Harte
b3bdfa9f46 Corrected: it's three-cycle 65C02 branches that ignore interrupts, not two. 2018-08-16 20:47:49 -04:00
Thomas Harte
592ec69d36 Causes the 65C02 not to accept interrupts immediately after untaken branches. 2018-08-15 22:42:04 -04:00
Thomas Harte
60e00ddd02 Correction: the test for not skipping an operand fetch requires a 65C02. 2018-08-15 22:07:17 -04:00
Thomas Harte
6806193dc2 Ensures that "Read/Modify/Write instructions absolute indexed in same page" take only six cycles on a 65C02. 2018-08-15 19:17:37 -04:00
Thomas Harte
c35dca783f Ensures that page-crossing indexing no longer causes an extra read of an invalid address on the 65C02. 
It rereads the last byte of the instruction stream instead.
 2018-08-15 18:47:53 -04:00
Thomas Harte
901e0d65b9 Documents all 6502 micro-operations. 
Also makes sure 1-cycle NOPs really, definitely are one cycle only on a 65C02 and eliminates OperationCopyOperandFromA as a redundant copy of OperationSTA.
 2018-08-14 22:17:53 -04:00
Thomas Harte
ddf45a0010 Ensures NMI and RST reset D on 65C02s. 2018-08-14 19:49:14 -04:00
Thomas Harte
1eca4463b3 Ensures NMI can no longer usurp BRK on 65C02s. 2018-08-14 19:33:48 -04:00
Thomas Harte
be01203cc1 Starts to expand the range of supported 6502s. 
This fully implements the NES 6502 because, well, it's virtually no extra work, and ensures that RDY takes effect on write cycles on 65C02s.
 2018-08-13 22:17:22 -04:00
Thomas Harte
4b91910fab Removes erroneous addition. 2018-08-10 23:27:09 -04:00
Thomas Harte
878c63dcd2 Ensures ADC and SBC decimal take an extra cycle on the 65C02. 2018-08-10 22:52:55 -04:00
Thomas Harte
261fb3d4f8 Implements proper test for ADC/SBC 65C02 NZ, though not yet the proper timing. 
This gets Klaus Dorman's test to pass.
 2018-08-10 22:42:35 -04:00
Thomas Harte
5d6e479338 Implements RMB and SMB, and fixes SBC (zero). 2018-08-10 22:13:51 -04:00
Thomas Harte
90094529a5 Implements TSB and TRB, and adds the extra BIT instructions. 2018-08-10 22:04:45 -04:00
Thomas Harte
aed4c0539e Implements STZ. 2018-08-10 21:17:02 -04:00
Thomas Harte
8b50ab2593 Corrects (zero) behaviour. 2018-08-10 21:12:55 -04:00
Thomas Harte
95164b79c9 Attempted implementation of (zp) addressing mode. 2018-08-09 21:51:14 -04:00
Thomas Harte
6f838fe190 Implements INA and DEA. 2018-08-08 22:30:19 -04:00
Thomas Harte
bb680b40d8 Implements the 65C02's JMPs. 2018-08-08 22:26:57 -04:00
Thomas Harte
e3f6da6994 Implements the 65C02 NOPs. 2018-08-08 20:00:14 -04:00
Thomas Harte
e46bde35f5 Implements BBS and BBR. 2018-08-07 21:52:17 -04:00
Thomas Harte
32338bea4d Implements BRA. 2018-08-06 22:37:30 -04:00
Thomas Harte
5c881bd19d Implements PLX, PLY, PHX and PHY. 2018-08-06 22:00:23 -04:00
Thomas Harte
1a44ef0469 Introduces Klaus Dorman's 65C02 tests. All failing. 2018-08-06 21:48:43 -04:00
Thomas Harte
ebce9a2e51 Fixes test target. 2018-08-06 21:15:13 -04:00
Thomas Harte
633af4d404 The operations table is now per-instance. 2018-08-06 20:47:14 -04:00
Thomas Harte
76a73c835c Forces 6502 consumers to declare which model — the original, 65C02 or 65SC02. 
All present machines use a regular 6502.
 2018-08-06 20:06:07 -04:00
Thomas Harte
0b14850467 Corrects some comments. 2018-06-24 23:02:36 -04:00
Thomas Harte
9a91ae38c1 Differentiates reasons for a read to be four cycles. 
Specifically, puts the enforced wait either before or after checking the wait line. More research may be required; it feels more likely to me that a forced post wait should complete the read then wait, but would that still count as a single machine cycle?
 2018-06-20 21:34:21 -04:00
Thomas Harte
ad9b0cd4e3 Eliminates all endashes. 2018-05-13 15:43:03 -04:00
Thomas Harte
5d6b5d9f10 Eliminates all emdashes in cross-platform code. 2018-05-13 15:34:31 -04:00
Thomas Harte
0b771ce61a Removes all instances of the copyright symbol. 2018-05-13 15:19:52 -04:00
Thomas Harte
45be1c19df Resolves undefined behaviour of a signed shift left. 2018-03-22 21:59:39 -04:00
Thomas Harte
0e73ba4b3e Introduces proper 5/3 SCF/CCF behaviour for the Z80. 
While also `const`ing a bunch of things.
 2018-03-09 09:47:00 -05:00
Thomas Harte
f0f9d5a6af Corrects memptr leakage via BIT, and ld (de/bc/nn), A behaviour. 2018-03-08 20:30:22 -05:00
Thomas Harte
74dfe56d2b
Expands documentation of NMI setting. 
Given that it was previously incorrect, explains logic behind request_status_ and last_request_status_ setting. Also takes the opportunity to ensure that NMI is 'sampled' at the same time as IRQ; whether the next thing should be the NMI routine now occurs one cycle before the end of any instruction. That's an assumption for now. Testing to come.
 2018-03-02 11:10:02 -05:00
Thomas Harte
b02e4fbbf6 Corrects NMI receipt to be genuinely edge triggered. 
Previously a caller that signalled NMI set multiple times would trigger multiple NMIs.
 2018-03-01 22:04:56 -05:00