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Commit Graph

18 Commits

Author SHA1 Message Date
Thomas Harte 70c4d6b9b3 Adds a one second delay between controller and drive motor off. 2018-08-03 21:13:18 -04:00
Thomas Harte 98bb5bd9f1 Ensures flux bits are observable for two cycles rather than one; it should be 1us. 2018-07-31 23:01:11 -04:00
Thomas Harte dde9b73a22 Creates the through-path that will be necessary for RWTS acceleration. 2018-06-09 12:51:53 -04:00
Thomas Harte 928aab13dc Introduces more granular clocking announcements to the Disk II.
As well as making it accept the clock rate it'll actually receive, to supply to the drives, so that they spin at the proper speed.
2018-05-28 17:19:29 -04:00
Thomas Harte db8d8d8404 Commutes Sleeper to ClockingHint::Source, making state more granular. 2018-05-27 23:17:06 -04:00
Thomas Harte e482929da8 Enhances the Disk II's ability to sleep.
Also enables Disk II sleep observation in the Oric.
2018-05-19 23:15:28 -04:00
Thomas Harte 7b7beb13a3 Eliminates the fiction of setting and getting registers.
The Disk II seems lower level than that; it will read the data bus whenever it likes, it is the programmer's responsibility to keep up with that. It also reserves the right not to load the bus regardless of whether it receives a read or write access.
2018-05-17 21:39:11 -04:00
Thomas Harte 8a031b1137 Eliminates 'data' register as it doesn't exist; rejigs state machine command set. 2018-05-16 22:09:59 -04:00
Thomas Harte 4c49963988 Switches to proper handling of the motor control and write protection.
Per Understanding the Apple II the drive looks write protected  while phase 1 is enabled.
2018-05-16 21:44:09 -04:00
Thomas Harte 0b771ce61a Removes all instances of the copyright symbol. 2018-05-13 15:19:52 -04:00
Thomas Harte a43ca0db35 Makes the Apple II an activity source. 2018-05-10 22:17:13 -04:00
Thomas Harte c3144382c5 Shuffles the Disk II ROM at load time into B.A.P. form.
Only if required. In order to support various potential forms of supplied ROM.
2018-05-09 22:03:59 -04:00
Thomas Harte c3a2f7717b Makes attempt to implement support for the Pravetz 8D + 8DOS.
i.e. the Disk II wired up to the Oric, with some ROM swaps.
2018-05-08 22:05:43 -04:00
Thomas Harte 10c0e687f5 Attempts to introduce sleeping for the Disk II. 2018-04-29 17:51:10 -04:00
Thomas Harte 7061537ff5 Makes joined-up attempt to run data through the Disk II. 2018-04-24 19:44:45 -07:00
Thomas Harte af61bbc3e2 Attempts actual performance of the state machine. 2018-04-24 08:29:05 -07:00
Thomas Harte 56d88f23ef Teeters closer and closer to trying actually to run the Disk II state machine. 2018-04-23 22:29:36 -07:00
Thomas Harte 72bc5f8d7b Adds a class to contain the Disk II and begins Apple GCR conversion routines. 2018-04-21 14:33:42 -07:00