Thomas Harte
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ce98ca4bdd
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Pull RO[L/R][X]m out of their macro stupor.
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2022-10-17 11:27:04 -04:00 |
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Thomas Harte
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cc55f0586d
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Clean up ASL/ASR/LSL/LSRm.
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2022-10-17 11:18:10 -04:00 |
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Thomas Harte
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47e8f3c0f1
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Collapse [A/L]S[L/R].[bwl] into a template.
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2022-10-16 22:21:20 -04:00 |
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Thomas Harte
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d5ceb934d2
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Fix overflow flags, avoid bigger-word usage.
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2022-10-16 21:52:00 -04:00 |
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Thomas Harte
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17c1e51231
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Commute ROL/ROR to templates.
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2022-10-16 12:19:09 -04:00 |
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Thomas Harte
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fee072b404
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Commute ROXL and ROXR into a template.
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2022-10-16 12:06:28 -04:00 |
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Thomas Harte
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0a9c392371
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Remove unused bit_count .
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2022-10-13 15:01:06 -04:00 |
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Thomas Harte
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06dbb7167b
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Unify TST.
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2022-10-11 21:31:14 -04:00 |
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Thomas Harte
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eff9a09b9f
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Collapse MOVE and NEG[X] similarities.
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2022-10-11 21:27:18 -04:00 |
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Thomas Harte
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1f19141746
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Eliminate BiggerInt .
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2022-10-11 16:19:47 -04:00 |
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Thomas Harte
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28093196b9
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Convert DIVU/DIVS logic to a template.
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2022-10-11 16:16:53 -04:00 |
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Thomas Harte
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eb206a08d9
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Templatise MULU/MULS.
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2022-10-11 16:02:20 -04:00 |
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Thomas Harte
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b2f005da1b
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Collapse SR/CCR bitwise operations into a template.
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2022-10-11 15:53:11 -04:00 |
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Thomas Harte
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8305a3b46a
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Consolidate compare logic.
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2022-10-11 12:57:02 -04:00 |
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Thomas Harte
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f3f23f90a3
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Consolidate repetition in CLR.
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2022-10-11 11:22:34 -04:00 |
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Thomas Harte
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77bc60bf86
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Consolidate BCLR, BCHG and BSET into a macro.
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2022-10-11 10:47:55 -04:00 |
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Thomas Harte
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ec5d57fefe
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Eliminate 64-bit work.
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2022-10-11 10:33:28 -04:00 |
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Thomas Harte
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58396f0c52
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Perform a prima facie conversion of ADD/SUB[/X] from macros to templates.
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2022-10-10 22:21:13 -04:00 |
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Thomas Harte
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c3b436fe96
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Use int64_t as an intermediary to avoid x86 exception on INT_MIN/-1.
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2022-06-02 21:39:52 -04:00 |
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Thomas Harte
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659e4f6987
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Include fixed cost of rolls. Which includes providing slightly more information to did_shift .
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2022-06-01 20:30:51 -04:00 |
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Thomas Harte
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8ffaf1a8e4
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Ensure did_divu/s are performed even upon divide by zero.
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2022-05-29 21:18:19 -04:00 |
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Thomas Harte
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7788a109b0
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Tweak more overtly to avoid divide by zero.
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2022-05-29 20:51:50 -04:00 |
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Thomas Harte
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9e3c2b68d7
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Eliminate potential future implicit conversion warnings.
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2022-05-24 11:05:24 -04:00 |
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Thomas Harte
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cb77519af8
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Make BSR operate like the other offsets: the flow controller gets whatever was in the opcode.
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2022-05-20 12:40:09 -04:00 |
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Thomas Harte
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452dd3ccfd
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Add a performer call-out for Scc; use it to implement proper timing in the mk2 68000.
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2022-05-20 11:20:23 -04:00 |
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Thomas Harte
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acb63a1307
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Pull generalised DIVU/DIVS into a macro.
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2022-05-15 20:01:51 -04:00 |
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Thomas Harte
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341bf2e480
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Repattern DIVS after DIVU.
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2022-05-15 16:54:58 -04:00 |
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Thomas Harte
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f83954f5b7
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Switch to common bit-selection logic.
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2022-05-13 15:08:15 -04:00 |
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Thomas Harte
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6d43576db7
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Remove errant semicolon.
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2022-05-12 16:21:36 -04:00 |
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Thomas Harte
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b7d1bff0c7
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Eliminate branches from ABCD.
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2022-05-12 15:25:01 -04:00 |
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Thomas Harte
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79c5af755f
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Eliminate branches from SBCD.
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2022-05-12 15:18:03 -04:00 |
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Thomas Harte
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c6d84e7e60
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Use Status::FlagT pervasively.
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2022-05-12 11:42:33 -04:00 |
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Thomas Harte
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192513656a
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After much guesswork, fix SBCD and thereby pass flamewing tests.
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2022-05-12 11:39:01 -04:00 |
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Thomas Harte
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f3c1b1f052
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Name flags, remove closing underscores on exposed data fields.
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2022-05-12 08:19:41 -04:00 |
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Thomas Harte
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bd61c72007
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Mutate SBCD to correct values, though not yet statuses.
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2022-05-12 07:22:26 -04:00 |
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Thomas Harte
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0efeea1294
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Slightly improve SBCD. Not there yet though.
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2022-05-12 07:07:21 -04:00 |
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Thomas Harte
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a9902fc817
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Fix ABCD when the result has an invalid lower digit.
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2022-05-11 16:31:27 -04:00 |
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Thomas Harte
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943c924382
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Add missing: MOVE to/from USP, RESET.
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2022-05-11 07:52:23 -04:00 |
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Thomas Harte
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4b97427937
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Remove further magic constants.
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2022-05-11 07:00:35 -04:00 |
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Thomas Harte
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c635720a09
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Tidy up; provide a notification for bit-change operations.
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2022-05-10 08:23:25 -04:00 |
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Thomas Harte
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f2a6a12f79
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Remove further vestiges of timing.
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2022-05-09 20:58:51 -04:00 |
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Thomas Harte
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7445c617bc
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Start removing 68000-specific timing calculations.
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2022-05-09 20:32:02 -04:00 |
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Thomas Harte
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2ca1eb4cf8
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Move set_pc into the operation-specific group.
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2022-05-09 16:20:15 -04:00 |
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Thomas Harte
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0af8660181
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Remove add_pc and decline_branch in favour of operation-specific signals.
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2022-05-09 16:19:25 -04:00 |
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Thomas Harte
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2f7cff84d9
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Enable missing rotates and shifts.
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2022-05-09 11:26:01 -04:00 |
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Thomas Harte
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0818fd7828
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Ensure no status updates fall through the cracks.
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2022-05-07 21:29:12 -04:00 |
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Thomas Harte
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bf8c97abbb
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Permit TRAP, TRAPV and CHK to push the next PC rather than the current.
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2022-05-07 20:32:39 -04:00 |
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Thomas Harte
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2b3900fd14
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Fix LINK A7.
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2022-05-07 08:15:26 -04:00 |
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Thomas Harte
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1defeca1ad
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Implement RTS, RTR, RTE.
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2022-05-06 12:30:49 -04:00 |
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Thomas Harte
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ac6a9ab631
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Fix TAS Dn.
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2022-05-06 12:23:04 -04:00 |
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