Thomas Harte
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a5d0976c2d
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Eliminate unused #includes.
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2021-07-18 11:35:57 -04:00 |
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Thomas Harte
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ae05010255
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Improve indentation.
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2021-07-18 11:29:26 -04:00 |
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Thomas Harte
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66cacbd0e0
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Be overt about the type being supplied.
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2021-07-18 11:28:18 -04:00 |
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Thomas Harte
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8e242eea54
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Ensures timer-linked PB7 output is actually output.
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2020-09-20 15:03:26 -04:00 |
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Thomas Harte
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703065a0a5
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Takes a run at timer-linked PB7 output behaviour.
Seemingly sufficiently to pass the VICE test (which I've transcribed), though with some guesswork.
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2020-09-20 14:51:59 -04:00 |
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Thomas Harte
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267006782f
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Starts to add Qt target; resolves many build warnings.
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2020-05-30 00:37:06 -04:00 |
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Thomas Harte
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31c6faf3c8
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Adds a bunch of consts.
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2020-05-09 21:23:52 -04:00 |
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Thomas Harte
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c1bae49a92
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Standardises on read and write for bus accesses.
Logic being: name these things for the bus action they model, not the effect they have.
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2020-01-05 13:40:02 -05:00 |
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Thomas Harte
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9230969f43
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Corrects enough of the 6522 and Keyboard to get an initial command seemingly working.
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2019-06-10 09:28:27 -04:00 |
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Thomas Harte
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723137c0d4
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With some time additions to the 6522, starts wiring in Macintosh audio.
The audio buffer is also the disk motor buffer, so this is preparatory to further disk work.
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2019-06-01 14:39:40 -04:00 |
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Thomas Harte
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2e7bc0b98a
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Attempts the shift register.
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2019-05-08 14:54:40 -04:00 |
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Thomas Harte
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8278809383
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Attempts to get more rigorous on communicating outward control line changes.
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2019-05-08 13:33:22 -04:00 |
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Thomas Harte
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4367459cf2
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Takes a first go at handshake and pulse modes.
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2019-05-08 12:48:29 -04:00 |
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Thomas Harte
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254132b83d
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Eliminates 6522Base in pursuit of working handshake modes.
Specifically: this means that the places from which the BusHandler may be called are more numerous.
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2019-05-08 12:35:17 -04:00 |
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Thomas Harte
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d97348dd38
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Eliminates dangling uses of printf.
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2019-03-02 18:07:05 -05:00 |
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Thomas Harte
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0b771ce61a
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Removes all instances of the copyright symbol.
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2018-05-13 15:19:52 -04:00 |
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Thomas Harte
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bc464e247f
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The 1540 and, by extension, the Vic-20 are now activity sources.
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2018-05-11 22:24:33 -04:00 |
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Thomas Harte
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ff510f3b84
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Explicitly disallows copying of VIAs, and marks the constructor as noexcept.
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2017-09-05 21:21:23 -04:00 |
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Thomas Harte
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450712f39c
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Improves and corrects 6522 header documentation.
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2017-09-04 14:32:34 -04:00 |
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Thomas Harte
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24b3faa427
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Deconstitutes the 6522 into component parts, templated and non-templated.
Adjusts the Oric, Vic-20 and C-1540 accordingly, albeit with the quickest possible solutions.
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2017-09-04 14:26:04 -04:00 |
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Thomas Harte
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4abd62e62b
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Standardises on const [Half]Cycles as the thing called and returned, rather than const [Half]Cycles & as it's explicitly defined to be only one int in size, so using a reference is overly weighty.
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2017-07-27 22:05:29 -04:00 |
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Thomas Harte
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1da24d10fd
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Corrected a couple of build errors.
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2017-07-27 08:05:14 -04:00 |
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Thomas Harte
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8361756dc4
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Switched definitively to the works-for-now approach of requiring an explicit opt-in where somebody wants to clock a whole-cycle receiver from a half-cycle clock.
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2017-07-27 07:40:02 -04:00 |
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Thomas Harte
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75d67ee770
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Relocated ClockReceiver.hpp as it's a dependency for parts of the static analyser, and therefore needs to be distinct from the actual emulation parts.
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2017-07-25 20:20:55 -04:00 |
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Thomas Harte
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efdac2ce8c
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The 6522 is now a ClockReceiver.
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2017-07-24 22:29:09 -04:00 |
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Thomas Harte
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e01f3f06c8
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Completed curly bracket movement.
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2017-03-26 14:34:47 -04:00 |
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Thomas Harte
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36bc558798
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Converted all 'Components' to postfix underscores.
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2016-12-03 10:51:09 -05:00 |
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Thomas Harte
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fa65cc2058
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Resolved type conversion error.
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2016-11-05 12:57:01 -04:00 |
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Thomas Harte
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30c670f8de
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Ensured programmatic setting of the timers occurs during phase 2 _instead_ of counting.
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2016-11-04 21:30:18 -04:00 |
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Thomas Harte
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ad00304e8a
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Fixed 6522 countdown.
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2016-10-28 21:05:42 -04:00 |
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Thomas Harte
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4fab794747
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Added a direct-to-two-cycles emulation path for 6522 owners.
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2016-10-27 21:13:25 -04:00 |
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Thomas Harte
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2eda0b3c86
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Attempted to simplify the logic behind the most common 6522 usage.
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2016-10-27 21:06:31 -04:00 |
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Thomas Harte
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b43a7381ae
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Fixed framing and first-byte-after-sync signalling. Hacked together as parts of it are, loading now appears to work!
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2016-08-01 04:25:11 -04:00 |
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Thomas Harte
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11cd541786
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Fixed accidental indentation.
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2016-07-10 08:05:05 -04:00 |
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Thomas Harte
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c0ab45a73d
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Disabled a bunch of the caveman debug logging.
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2016-07-09 22:29:11 -04:00 |
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Thomas Harte
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7cc4bf3fe7
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Hit and hope is getting me nowhere. Time to unit test this thing.
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2016-07-09 15:40:25 -04:00 |
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Thomas Harte
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1baf21827c
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Since the ROM is well disassembled, let's actually try to be a 1541 first.
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2016-07-06 22:17:32 -04:00 |
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Thomas Harte
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8819711bc8
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Threw in the second VIA as a currently clearly incorrect thing.
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2016-07-05 22:22:09 -04:00 |
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Thomas Harte
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602e7f01c7
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Control lines seem to have evolved to pure push.
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2016-07-05 21:15:29 -04:00 |
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Thomas Harte
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93c2bb80a2
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Improved a comment, added independent C[A/B]2 input mode.
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2016-07-05 21:11:51 -04:00 |
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Thomas Harte
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1bb109a23b
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Made a quick attempt at basic C[A/B]2 interrupts.
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2016-07-05 20:39:15 -04:00 |
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Thomas Harte
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c3b7d24293
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It appears that the attention line is also wired to CB2. So the ball is back in the 6522's court.
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2016-07-05 19:19:46 -04:00 |
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Thomas Harte
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97751a9d86
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Took the preliminary steps necessary to wire up a serial port.
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2016-07-05 10:55:47 -04:00 |
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Thomas Harte
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82b0bc9b58
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Discovered that this is another meaningful usage of using.
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2016-07-04 19:10:10 -04:00 |
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Thomas Harte
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7fa010a463
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Attempted to add support for the most basic of control line output, and slightly to optimise the Vic.
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2016-07-01 19:01:22 -04:00 |
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Thomas Harte
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69d78dfdb3
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Removed logging.
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2016-06-26 21:36:26 -04:00 |
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Thomas Harte
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843d1fdca7
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Added some extra logging while trying to determine what's going on; added interrupt clearing for the control lines.
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2016-06-26 21:30:06 -04:00 |
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Thomas Harte
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c306d705e1
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Made a quick first attempt at all-the-way-through tape wiring for the Vic.
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2016-06-26 19:43:09 -04:00 |
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Thomas Harte
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37ba42a52f
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Factored out the stuff of playing a tape, started basic sketch of the Vic-related classes.
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2016-06-26 19:03:57 -04:00 |
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Thomas Harte
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066db59773
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Made a hasty attempt to implement CA1 and CB1 input as a potential source of interrupts.
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2016-06-26 16:32:27 -04:00 |
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