6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2024-11-23 03:32:32 +00:00
Code Issues Projects Releases Wiki Activity
5,133 Commits 8 Branches 121 Tags 496 MiB
de3c8373fd
Commit Graph

700 Commits

Author SHA1 Message Date
Thomas Harte
9bc09046c0 Attempts to ensure that sprites can go off the top of the screen. 2018-10-18 21:48:57 -04:00
Thomas Harte
512f085891 Ensures proper left clipping of sprites. 2018-10-18 21:14:16 -04:00
Thomas Harte
da00c832f5 Corrects colour fetching for multicolour text mode. 2018-10-18 20:38:00 -04:00
Thomas Harte
8ff265c3a1 Corrects multicolour text mode. 2018-10-18 20:25:42 -04:00
Thomas Harte
1fc88c4eff Corrects off-by-one error in line fetching coroutines. 2018-10-16 21:36:31 -04:00
Thomas Harte
58ca74c68a Resolves right-side TMS sprite droppages. 2018-10-16 21:25:08 -04:00
Thomas Harte
b4f871a2ef Corrects first line sprite row selection. 2018-10-16 21:16:29 -04:00
Thomas Harte
0f7bf6d6c6 Resolves attempt to output graphics on the line one before the display. 2018-10-16 21:02:31 -04:00
Thomas Harte
5dfe7d8596 Corrects most of TMS sprite drawing. 2018-10-16 20:49:04 -04:00
Thomas Harte
231009b901 Makes faulty attempt to reintroduce TMS-mode sprites. 2018-10-16 20:00:06 -04:00
Thomas Harte
1c5f939aea Reintroduces tiles and some element of sprites in regular TMS mode. 2018-10-14 21:52:13 -04:00
Thomas Harte
c1e6406fc9 Corrects sprite accumulation. 2018-10-14 19:56:09 -04:00
Thomas Harte
d66979c68f Switched to a very large number of buffers, and resolved stupid attempt to reassign a reference. 2018-10-14 18:19:11 -04:00
Thomas Harte
6c09abc6cb Makes a flawed attempt to reformulate this exactly as two separate processes on a common clock with an interchange buffer. 
Specifically because closer inspection of the TMS modes shows it isn't quite valid to model output of one line as having fully completed prior to fetching of the next. So some sort of extra buffer is required. At which point it is most natural to continue with the logic that each fetch routine is oriented around the fetching process for a single line, and each output routine has the same view, suggesting separate read/write addresses.

Something is wrong though, as video data is being output too rapidly (I think) and with occasional sync issues (again: subject to investigation).
 2018-10-14 16:23:45 -04:00
Thomas Harte
9e52ead09a Ensures sprite scanning doesn't improperly set collision flag; that slot 151 is filled. 2018-10-12 19:50:48 -04:00
Thomas Harte
9ab0c54426 Eliminates faulty attempt to satisfy SMSVDP vertical counter test. 2018-10-12 18:57:07 -04:00
Thomas Harte
f6af6778ab Moves scrolling latch to proper position and implements 4-window fetching offset. 2018-10-11 22:36:27 -04:00
Thomas Harte
6a94dda60d Selects potentially-correct interrupt times. 2018-10-11 21:42:09 -04:00
Thomas Harte
82b7944599 Fixes horizontal counter wrapping. 2018-10-11 20:37:29 -04:00
Thomas Harte
52e02db5c8 Introduces horizontal counter latching and reading. 
Then makes a new guess at frame IRQ position. But gets it wrong. Hmmm.
 2018-10-11 19:56:32 -04:00
Thomas Harte
9a933993f5 Added TODO. 2018-10-10 22:17:17 -04:00
Thomas Harte
062b2ae8d3 Corrects calculation of [NTSC, 192 line] current row. 2018-10-10 22:15:38 -04:00
Thomas Harte
9f69dbf31a Adds half-updating of RAM pointer. 
This emulator now passes the first screen of the SMS VDP test.
 2018-10-10 21:59:08 -04:00
Thomas Harte
63fb3f03d1 Corrects address loading upon accesses of registers other than 0. 2018-10-10 21:47:48 -04:00
Thomas Harte
2e379b0834 Adds latching of scroll values. 2018-10-10 21:28:18 -04:00
Thomas Harte
f00f6c8c23 Allows the frame interrupt to be placed anywhere in the frame. 2018-10-10 21:07:39 -04:00
Thomas Harte
50e23f4a2e Fixes 16px-high sprites. 2018-10-10 20:34:00 -04:00
Thomas Harte
acdc84e08c Improves test slightly, and fixes line interrupt reload value setting. 2018-10-09 22:14:35 -04:00
Thomas Harte
c128ddb549 Introduces a first unit test for line interrupts and corrects backup behaviour. 2018-10-09 21:49:21 -04:00
Thomas Harte
dccf17e770 Makes a first serious attempt at Master System line interrupts. 2018-10-09 20:51:09 -04:00
Thomas Harte
2d8ab72e22 Fixed proper starting position for (interrupted) tile drawing. 2018-10-08 23:13:37 -04:00
Thomas Harte
748366c70e Corrects buffer overrun when the horizontal scroll lock is on. 2018-10-08 23:06:22 -04:00
Thomas Harte
7a74fe2ff7 Corrects tile plotting window and eliminates a redundant local. 2018-10-08 22:56:31 -04:00
Thomas Harte
e410302237 Switches to real SMS line output composition. 
Including setting the sprite collision bit.
 2018-10-08 22:43:10 -04:00
Thomas Harte
bca2161a05 Fixes TMS text mode for the new addressing order. 2018-10-07 21:09:01 -04:00
Thomas Harte
5f789092be Flips sprite priority in the temporary renderer. 
The better to test other issues in the interim.
 2018-10-07 19:16:35 -04:00
Thomas Harte
6975ed22c0 Doubles down on address-storage format, and implements the vertical scrolling lock. 2018-10-07 18:55:35 -04:00
Thomas Harte
3bead07043 Introduces proper indirection for sprite patterns. 
This seems to work, so the onus is now back on the rendering loop.
 2018-10-07 17:15:42 -04:00
Thomas Harte
ee20e42372 Makes initial attempt at collecting sprite contents. 
With test plotting, indicating some sort of issue.
 2018-10-07 16:53:25 -04:00
Thomas Harte
df411b4ede Corrects storage of visible sprites. 2018-10-07 16:40:32 -04:00
Thomas Harte
bfb9d8ccb6 At least attempts to use proper addressing for sprite info fetches. 2018-10-07 14:32:20 -04:00
Thomas Harte
338aec2930 Groups background fetches and experimentally seeks to daub sprites as white. 2018-10-06 22:07:04 -04:00
Thomas Harte
e6510dc87b Attempts to get at least as far as picking visible sprite indices. 2018-10-06 19:27:19 -04:00
Thomas Harte
7830cda912 Implements line querying and most of line interrupts. 2018-10-04 22:50:35 -04:00
Thomas Harte
aac97a8983 Re-revokes fine scroll on the top two lines when requested. 2018-10-04 19:18:15 -04:00
Thomas Harte
ca26dfcd61 Correct Master System palette writes. 2018-10-04 19:12:31 -04:00
Thomas Harte
858721a7a5 Added left border hiding. 2018-10-04 18:52:23 -04:00
Thomas Harte
89db1d6a6a Switches to a more accurate means of left-padding. 2018-10-04 18:44:49 -04:00
Thomas Harte
de4e5c40aa Implements horizontal scrolling lock. 2018-10-03 23:28:33 -04:00
Thomas Harte
05248ab990 Starts to reimplement Master System output. 2018-10-03 23:13:21 -04:00
Thomas Harte
252f47a425 Ensures no pixel output on line one before end, and adds a temporary debugging test. 2018-10-02 22:59:20 -04:00
Thomas Harte
be52b31b5c Attempts fully to revive text mode. 2018-10-02 22:05:58 -04:00
Thomas Harte
23c3fa6993 Fixed: it's the SMS that has 8 sprites, not text mode (which has none). 2018-10-02 22:01:43 -04:00
Thomas Harte
499fc62187 Sets things up for implementation of the inner mode-specific logic. 2018-10-02 21:58:09 -04:00
Thomas Harte
1dd5272190 Ensures real-time output of all areas, to ensure proper palette response. 2018-10-02 21:18:28 -04:00
Thomas Harte
5361120353 Restores a stable frame. 2018-10-02 21:05:30 -04:00
Thomas Harte
60bab8fdf1 Starts to reformulate TMS collection as coroutines. 
For the time being, thereby breaks all video. A static screen of the border colour is all you'll see.
 2018-10-01 23:03:17 -04:00
Thomas Harte
91aa8f9295 Amps up colour content a little. 2018-09-30 20:47:26 -04:00
Thomas Harte
23191efc05 Starts writing and referring to colour RAM for colours. 2018-09-29 19:50:13 -04:00
Thomas Harte
0d8af010b6 Takes a stab at tile reversal and vertical scrolling. 2018-09-28 22:37:10 -04:00
Thomas Harte
7b9bb772ca Corrected to give a not-exactly-indexed-correctly approximation of what's on display. 2018-09-28 21:03:51 -04:00
Thomas Harte
f7e211c245 Makes first attempt to put something vaguely like the Master System tile map on screen. 2018-09-28 20:39:14 -04:00
Thomas Harte
35c2e74af8 Attempts to establish a coroutine-ish structure for access patterns. 
The Master System mode, inevitably, is the test case.
 2018-09-27 22:33:41 -04:00
Thomas Harte
19482a563f Attempts to explicitly make room for the SMS VDP mode. 2018-09-27 21:22:57 -04:00
Thomas Harte
9683c8f664 Advances towards the Master System actually receiving interrupts. 2018-09-23 15:58:23 -04:00
Thomas Harte
e7f4babf41 Starts taking steps towards SMS/GG and V9938/9958 support. 
Specifically: routine namespace stuff, plus the intention to move to a table-based operation+cost version of timing. Reordering works fine for the TMS, and probably would also for the SMS/GG, but it'd be problematic with the command engine of the V9938/9958 and maintaining a consistent set of code is easier.
 2018-09-17 22:59:16 -04:00
Thomas Harte
a38639d099 Eliminates the concept of an iCoordinate. 
Real-life precision appears not to support the idea of sub-sample pixel storage.
 2018-09-12 20:05:39 -04:00
Thomas Harte
31b048f966 Ensures all bools start in a valid state. 2018-09-10 22:21:03 -04:00
Thomas Harte
7b9c1bb69c Makes minor layout improvements. 2018-09-09 21:02:31 -04:00
Thomas Harte
70c4d6b9b3 Adds a one second delay between controller and drive motor off. 2018-08-03 21:13:18 -04:00
Thomas Harte
98bb5bd9f1 Ensures flux bits are observable for two cycles rather than one; it should be 1us. 2018-07-31 23:01:11 -04:00
Thomas Harte
92065813ef Ensures only the first 8px of sprites is output in 8x8 mode. 
Also adds a little extra documentation.
 2018-07-15 22:21:29 -04:00
Thomas Harte
cd464fc7de Corrects status logging. 2018-06-26 20:53:08 -04:00
Thomas Harte
df8c896193 Removes unused state and implements AND output readback. 2018-06-26 19:31:16 -04:00
Thomas Harte
59f8eeb05a Ensures the AY goes high impedance when not in read mode. 2018-06-25 20:48:24 -04:00
Thomas Harte
5ab4cfee84 Factors out repeated hex-size setting. 2018-06-21 19:27:54 -04:00
Thomas Harte
a9eb0d02c6 Returns sanity to 8272 logging. 2018-06-20 23:02:32 -04:00
Thomas Harte
adca862166 Finally makes an initial pass at logging macros. 2018-06-18 22:37:19 -04:00
Thomas Harte
dde9b73a22 Creates the through-path that will be necessary for RWTS acceleration. 2018-06-09 12:51:53 -04:00
Thomas Harte
076fa55651 Corrects: flux set is no-flux incoming. 
This restores good sleeping behaviour.
 2018-06-03 08:11:17 -04:00
Thomas Harte
1a9cea050e Minor: ensure AY registers *read* as 0 from reset, as well as being 0. 2018-06-01 19:48:42 -04:00
Thomas Harte
35e84ff1a8 Corrects NTSC quadrature phase. 2018-05-31 21:40:46 -04:00
Thomas Harte
75f9e3caeb Resolves incorrect bracketing. 2018-05-28 17:48:35 -04:00
Thomas Harte
928aab13dc Introduces more granular clocking announcements to the Disk II. 
As well as making it accept the clock rate it'll actually receive, to supply to the drives, so that they spin at the proper speed.
 2018-05-28 17:19:29 -04:00
Thomas Harte
db8d8d8404 Commutes Sleeper to ClockingHint::Source, making state more granular. 2018-05-27 23:17:06 -04:00
Thomas Harte
086b801c29 Mildly rearranges to avoid unnecessary call. 2018-05-22 21:50:07 -04:00
Thomas Harte
e482929da8 Enhances the Disk II's ability to sleep. 
Also enables Disk II sleep observation in the Oric.
 2018-05-19 23:15:28 -04:00
Thomas Harte
ed06533e60 Implements write support out of the Disk II. 2018-05-18 22:07:58 -04:00
Thomas Harte
7b7beb13a3 Eliminates the fiction of setting and getting registers. 
The Disk II seems lower level than that; it will read the data bus whenever it likes, it is the programmer's responsibility to keep up with that. It also reserves the right not to load the bus regardless of whether it receives a read or write access.
 2018-05-17 21:39:11 -04:00
Thomas Harte
c46007332a Switches to returning the shift register contents on every even read. 2018-05-17 20:18:34 -04:00
Thomas Harte
908d3b0ee5 Slightly wrong as to the details, but gets the controller trying to output. 
At an initial look, I think the shift register should end up on the data bus for all odd accesses. Need to investigate more thoroughly.
 2018-05-16 22:37:22 -04:00
Thomas Harte
8a031b1137 Eliminates 'data' register as it doesn't exist; rejigs state machine command set. 2018-05-16 22:09:59 -04:00
Thomas Harte
1aba9f807e Ensures proper upward propagation of sleeping from first start. 2018-05-16 22:07:54 -04:00
Thomas Harte
4c49963988 Switches to proper handling of the motor control and write protection. 
Per Understanding the Apple II the drive looks write protected  while phase 1 is enabled.
 2018-05-16 21:44:09 -04:00
Thomas Harte
ad9b0cd4e3 Eliminates all endashes. 2018-05-13 15:43:03 -04:00
Thomas Harte
5d6b5d9f10 Eliminates all emdashes in cross-platform code. 2018-05-13 15:34:31 -04:00
Thomas Harte
0b771ce61a Removes all instances of the copyright symbol. 2018-05-13 15:19:52 -04:00
Thomas Harte
d703328114 Adds missing #include for memcpy. 2018-05-12 17:54:13 -04:00
Thomas Harte
bc464e247f The 1540 and, by extension, the Vic-20 are now activity sources. 2018-05-11 22:24:33 -04:00
Thomas Harte
a43ca0db35 Makes the Apple II an activity source. 2018-05-10 22:17:13 -04:00
Thomas Harte
c3144382c5 Shuffles the Disk II ROM at load time into B.A.P. form. 
Only if required. In order to support various potential forms of supplied ROM.
 2018-05-09 22:03:59 -04:00
Thomas Harte
c3a2f7717b Makes attempt to implement support for the Pravetz 8D + 8DOS. 
i.e. the Disk II wired up to the Oric, with some ROM swaps.
 2018-05-08 22:05:43 -04:00
Thomas Harte
f65c65569a Makes disk head position explicitly something with sub-integral precision. 
Also as a drive-by fix, corrects accidental assumption of 10 sectors for all MFMSectorDump descendants.
 2018-05-06 23:17:36 -04:00
Thomas Harte
aacf26f05d Removed logged comment. 2018-04-30 22:03:09 -04:00
Thomas Harte
10c0e687f5 Attempts to introduce sleeping for the Disk II. 2018-04-29 17:51:10 -04:00
Thomas Harte
41075356e2 Makes a first attempt at NIB support. 2018-04-26 22:49:07 -04:00
Thomas Harte
d59db504a3 Adjusted stepper logic; some disks load now. 2018-04-25 21:59:18 -04:00
Thomas Harte
4c6dc597f4 Converts Time::get into a template, introduces a via-a-double fallback for the timed event loop. 2018-04-25 19:54:39 -04:00
Thomas Harte
7061537ff5 Makes joined-up attempt to run data through the Disk II. 2018-04-24 19:44:45 -07:00
Thomas Harte
99de8f1c5c Inverts the pulse strobe. 2018-04-24 09:03:03 -07:00
Thomas Harte
af61bbc3e2 Attempts actual performance of the state machine. 2018-04-24 08:29:05 -07:00
Thomas Harte
56d88f23ef Teeters closer and closer to trying actually to run the Disk II state machine. 2018-04-23 22:29:36 -07:00
Thomas Harte
4bff44377a Attempts to route Disk II requests to the thing itself. 2018-04-23 22:11:31 -07:00
Thomas Harte
e87a3cffd4 Merge branch 'master' into DiskII 2018-04-21 15:02:18 -07:00
Thomas Harte
5968c9a391 Corrects Apple II output audio. 2018-04-21 14:56:50 -07:00
Thomas Harte
72bc5f8d7b Adds a class to contain the Disk II and begins Apple GCR conversion routines. 2018-04-21 14:33:42 -07:00
Thomas Harte
f22c23cb4c Attempts to bring audio to the Apple II. 
By factoring the audio toggle out from the MSX.
 2018-04-17 22:28:13 -04:00
Thomas Harte
1c605d58e3 Removes the CRT requirement for an integral relationship between cycles and samples. 2018-04-16 20:00:56 -04:00
Thomas Harte
467cd5450f Adjusts PAL Vic timing. 2018-04-12 21:12:09 -04:00
Thomas Harte
428b6145fa Converts 6560 to more project normative templated form. 2018-04-11 22:00:42 -04:00
Thomas Harte
4c8a68c6a4 Implements late-0 with proper timing, and NTSC interlaced raster count timing. 2018-04-11 08:00:37 -04:00
Thomas Harte
0b4b6f4aec Tweaks luminances and reintroduces late-to-zero line counts. 2018-04-10 23:05:18 -04:00
Thomas Harte
cf6f6c5c15 Eliminates the full_frame_counter_ and slightly tweaks NTSC raster timing. 2018-04-08 18:51:20 -04:00
Thomas Harte
f541986333 Switches to more normative preincrement. 2018-04-08 18:50:42 -04:00
Thomas Harte
1c5972f7b0 Ensures NTSC raster count rollover; previously it was positing a line '261' for half of '0'. 2018-04-08 16:18:41 -04:00
Thomas Harte
3e846f89a1 Introduces different clipping zones for NTSC and PAL output. 2018-04-05 21:25:19 -04:00
Thomas Harte
60c1da6a66 Causes the 6560 to obey set_sample_volume_range. 
Thereby resolves a clipping issue.
 2018-04-05 21:04:46 -04:00
Thomas Harte
0ee40e8556 Reintroduces 90% crop for VIC output. 2018-03-31 20:57:45 -04:00
Thomas Harte
912791d3d4 Causes the s-video path correctly to function. 2018-03-30 18:24:18 -04:00
Thomas Harte
163a61dd63 Corrects SVideo-as-composite output; the Atari and Vic-20 now both supply svideo. 2018-03-30 13:16:18 -04:00
Thomas Harte
33281b9d89 Introduces S-Video as a video signal type at the interface level. 2018-03-30 10:25:41 -04:00
Thomas Harte
e1aa3e5a7f Imports chrominances from the TED documentation. They seem to apply to the VIC-I also. 2018-03-29 20:04:37 -04:00
Thomas Harte
3b26e0a7c5 Tweaks NTSC colour generation. 2018-03-26 21:22:06 -04:00
Thomas Harte
a776bec46a Tweaks PAL colours for the 6560 to be closer to screenshots found online. 2018-03-26 19:02:16 -04:00
Thomas Harte
a301964bd0 Ensures all audio queues are fully merged before machine destruction. 
Thereby avoids a race condition.
 2018-03-22 21:59:19 -04:00
Thomas Harte
48737a32a7 Introduces formal setting of the output volume to SampleSource. 
Previously every output device was making its own decision. Which is increasingly less sustainable due to the CompoundSource.
 2018-03-09 13:23:18 -05:00
Thomas Harte
705d53cc21 Picks a phase for the TMS empirically. 2018-03-03 13:53:00 -05:00
Thomas Harte
3c5a8d9ff3 Adds Super Game Module support for the ColecoVision. 2018-03-03 13:08:33 -05:00
Thomas Harte
ea13c7dd32 Implements multicolour mode on the TMS. 2018-03-02 23:08:01 -05:00
Thomas Harte
86239469e7 Allows SN76489 consumers to apply an additional divider that reduces computation. 2018-03-01 18:51:05 -05:00
Thomas Harte
7890506b16 Gives the SN76489 its proper dividers and personalities. 2018-02-28 22:36:03 -05:00
Thomas Harte
5b854d51e7 Corrects out-of-bounds access. 2018-02-27 22:45:45 -05:00
Thomas Harte
d4df101ab6 Makes a first attempt at implementing the SN76489. 2018-02-27 22:25:12 -05:00
Thomas Harte
0ad2676640 Adds a class for the SN76489 and wires it into the ColecoVision. 2018-02-26 22:04:34 -05:00
Thomas Harte
cabad6fc05 Optimises the inner TMS loops slightly. 2018-02-21 21:29:17 -05:00
Thomas Harte
2fe0ceb52a Sets TMS input gamma. 2018-01-13 22:19:41 -05:00
Thomas Harte
2f59226300 Fixes: DiskROM drive motor control, track_for_sectors' sides. 2018-01-07 20:02:40 -05:00
Thomas Harte
793ef68206 Implements unconditional force interrupt for the WD. 2018-01-07 19:42:38 -05:00
Thomas Harte
2ffde4c3c2 Corrects SCC volume errors. 
Which were leading to substantial overflow.
 2018-01-07 09:59:00 -05:00
Thomas Harte
57ddfcd645 Corrects AY counter type. 2018-01-06 23:16:01 -05:00