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Author SHA1 Message Date
Thomas Harte
7476c64a66 Merge branch 'master' into BufferOverflow 2017-07-07 21:11:07 -04:00
Thomas Harte
46fff8e8a2 Ensured bit 8 is uniquely from the latched video byte, not an OR of that with the refresh address. 2017-07-06 22:48:48 -04:00
Thomas Harte
cd646aab9e Merge pull request #141 from TomHarte/ZX81FastLoading 
Corrects ZX81 fast loading
 2017-07-06 22:39:19 -04:00
Thomas Harte
a3684545b5 Added a block on the tape motor for a short period after each time the ROM routine is intercepted for a substituted byte read. To reduce the collision between fast tape and real tape loading. 2017-07-06 22:33:54 -04:00
Thomas Harte
2f42874fd3 Another fix to deal with real-time fighting: allow 8 and 18 pulses to be recognised as 1s and 0s. That's because the hand-off from ROM routines to parsing may occur very shortly before the first pulse of a valid sequence, making it look like there's a ghost. A cleaner solution needs to be found, probably revolving around allowing parsers to be attached to tapes and therefore to run constantly. 2017-07-06 22:33:03 -04:00
Thomas Harte
84d0e9b4cd Accept a pulse that begins exactly on seek_time as being found while seeking. 2017-07-06 22:31:45 -04:00
Thomas Harte
a53011f778 Extended intro and outro length because right now I'm racing this myself. Can return to normal once tape motor control is implemented. 2017-07-06 22:31:12 -04:00
Thomas Harte
b842c5b8bb Merge branch 'master' into ZX81FastLoading 2017-07-06 22:03:24 -04:00
Thomas Harte
ab1374f801 Added an assert on an assumed buffer size alignment. 2017-07-06 21:46:24 -04:00
Thomas Harte
a5359027f0 Merge pull request #140 from TomHarte/ColourSuppression 
Causes the CRT to react properly to absence of a colour burst
 2017-07-06 21:42:02 -04:00
Thomas Harte
43951a36eb Merge branch 'master' into ColourSuppression 2017-07-06 21:40:42 -04:00
Thomas Harte
55df96491c Merge pull request #139 from TomHarte/TyperFixes 
Corrects a potential invalid memory dereference in the default typer implementation
 2017-07-06 21:40:15 -04:00
Thomas Harte
0c037627fc Typer fixes: the recipient no longer releases the caller, and a duplicate call to strlen and piece of arithmetic is corrected. 2017-07-06 21:38:56 -04:00
Thomas Harte
344d267fd2 Introduced sharper chrominance for genuinely black-and-white signals. 2017-07-06 21:38:33 -04:00
Thomas Harte
4211389ac7 Connected machine-supplied colour burst amplitude to shader, discarding hard-coded value. Net effect: the colour component is now discarded for the ZX80 and 81. 2017-07-06 21:29:08 -04:00
Thomas Harte
c6d00ec7d1 Switched phase and amplitude varying to a 3d vector; the third component is 1/amplitude if amplitude is non-zero, and zero otherwise. So you can multiply by that to get chrominance, rather than dividing by amplitude. With the direct effect that detected chrominance should automatically be zero if the colour burst didn't exist (i.e. had zero amplitude). 2017-07-06 21:25:38 -04:00
Thomas Harte
212ae60622 Typer fixes: the recipient no longer releases the caller, and a duplicate call to strlen and piece of arithmetic is corrected. 2017-07-06 21:17:04 -04:00
Thomas Harte
a72a2e0a1a Ensured tape doesn't proceed of its own volition when in fast-loading mode. 2017-06-23 20:21:37 -04:00
Thomas Harte
50375fb373 Ensured tape position is unaffected if the attempt at loading quickly fails. 2017-06-23 20:18:19 -04:00
Thomas Harte
2d02c23574 Merge pull request #138 from TomHarte/ZX81Ports 
Increases port decoding on the ZX81
 2017-06-23 08:32:21 -04:00
Thomas Harte
cb105fdeb4 Took a first stab at high-res support. 2017-06-22 22:48:17 -04:00
Thomas Harte
acfd4dde36 Reduced port writes which can adjust programmatic sync, and prevented anything while NMI generation is active. Moved line counter increment from triggered by interrupt acknowledge to triggered by horizontal sync. In both cases, cribbing from my own earlier work. Initial results suggest that sync issues are resolved in third-party software. 2017-06-22 22:44:06 -04:00
Thomas Harte
919fc48cc5 Fixed dumb out-of-bounds access error. 2017-06-22 22:28:50 -04:00
Thomas Harte
aec4fd066b I think I've definitively decided against this model of timing. 2017-06-22 21:32:14 -04:00
Thomas Harte
73c7b18900 Added a public declaration of ZX80/81 support to the readme. 2017-06-22 21:14:43 -04:00
Thomas Harte
3dfe45d225 Merge pull request #137 from TomHarte/NMIWaitTest 
Introduces an NMI/wait interrupt timing test
 2017-06-22 21:11:54 -04:00
Thomas Harte
95a6b0f85c Introduced an NMI/wait interrupt timing test, and adjusted the Z80 to conform to information posted by Wilf Rigter. 2017-06-22 21:09:26 -04:00
Thomas Harte
87ee8450fe Minor rejig: it's much more likely that something that can't be distinguished is a ZX81 program. TODO: some sort of BASIC token parsing, to be more confident. 2017-06-22 20:23:14 -04:00
Thomas Harte
f2a6bcf2a8 Merge pull request #136 from TomHarte/ZX8081Options 
Finally adjusts ZX80/81 tape loading so that the fast loading hack is optional as per the GUI
 2017-06-22 20:21:28 -04:00
Thomas Harte
644ef13acd Connected up the fast-tape GUI option for the ZX80 and '81. 2017-06-22 20:20:31 -04:00
Thomas Harte
342574761f Merge pull request #135 from TomHarte/InterruptWaitStates 
Ensures wait states are observed during interrupt response
 2017-06-22 20:15:54 -04:00
Thomas Harte
b7c978e078 Added getters for most of the input lines, and attempted to round out the ZX81's wait logic. 2017-06-22 20:11:19 -04:00
Thomas Harte
f0398a6db8 Added wait state hooks to the interrupt programs, and added an is_wait query on PartialMachineCycle. 2017-06-22 20:07:47 -04:00
Thomas Harte
f3b1ef99cc Merge pull request #134 from TomHarte/BinaryTape 
Switches the binary tape player to low = false, high = true
 2017-06-21 22:25:42 -04:00
Thomas Harte
52d9ddf9e5 Gave the binary tape player a more logical assignment of wave level to output level. Which miraculously appears to have been the issue with the ZX80/81 tape loading — the inconsistency of silences seems to have been the issue. 2017-06-21 22:13:24 -04:00
Thomas Harte
93f251dbcd Merge pull request #133 from TomHarte/ZX81Wait 
Utilises the newly-working wait line in ZX81 emulation
 2017-06-21 21:46:08 -04:00
Thomas Harte
a6810fc3ef Removed some minor duplicity and ensured that hsync/NMI ends on the nominated cycle, not one afterwards. 2017-06-21 21:44:42 -04:00
Thomas Harte
15f6c51062 Added the most trivial implementation of the ZX81 wait line. 2017-06-21 21:28:14 -04:00
Thomas Harte
5e21c706f3 Merge pull request #132 from TomHarte/MachineCycles 
Subdivides the Z80's machine cycles
 2017-06-21 21:19:48 -04:00
Thomas Harte
e1355d4b62 Restored proper video output. 2017-06-21 21:18:09 -04:00
Thomas Harte
7eeac3b586 Switched R back to incrementing after the refresh cycle. It had snuck to before by virtue of subdivision of the M1 cycle. Which shortened the ZX80 line time, breaking synchronisation. 2017-06-21 21:11:00 -04:00
Thomas Harte
4bf13610ce Reinstated interrupts by moving the refresh test back into the refresh cycle. 2017-06-21 21:03:39 -04:00
Thomas Harte
0e0ce379b4 Renamed MachineCycle to PartialMachineCycle given that it mostly no longer intends to describe an entire machine cycle. 2017-06-21 20:38:08 -04:00
Thomas Harte
36e8a11505 Sought to simplify the way partial machine cycles are communicated, for ease of machine implementation. Also implemented the wait line. 2017-06-21 20:32:08 -04:00
Thomas Harte
45f442ea63 Corrected interrupt mode 2: was both failing properly to load the vector address, and failing to read from it. 2017-06-21 19:08:48 -04:00
Thomas Harte
db743c90d8 Had neglected to count refresh time in my interrupt programs. Corrected. Mode 0 timing test succeeds again. Only Mode 2 is now at fault. 2017-06-21 18:58:44 -04:00
Thomas Harte
10cc94f581 Attempted to fix interrupt response timing; ensured initial interrupt mode is one that won't jump beyond the interrupt response program table's length, and that the conditionals other than CALL definitely have no alternative program attached. 2017-06-21 18:47:00 -04:00
Thomas Harte
108da64562 Fixed LD H, (HL) and LD L, (HL) by ensuring that whatever the subclass does goes to a temporary place before updating the address. Corrected the LD (IX+d), n machine cycle test for my new best-guess timing. This should leave only interrupt timing as currently amiss. 2017-06-20 22:25:00 -04:00
Thomas Harte
f85b46286e Resolved the timing disparity between LD (HL),n and LD (IX+d), n, hopefully having come up with a convincing theory of timing for the latter. 2017-06-20 22:20:58 -04:00
Thomas Harte
184b371649 Attempted to get to 'proper' timing for LD (IX+d),n, albeit that proper is a guess. 2017-06-20 21:48:50 -04:00