5 Commits

Author	SHA1	Message	Date
Thomas Harte	941d9a46a2	Makes a better effort at exposition; better implements clocked line.	2021-11-07 05:18:40 -08:00
Thomas Harte	ecfe68d70f	Introduce the principle that a Serial::Line can be two-wire — clock + data.	2021-11-06 16:54:20 -07:00
Thomas Harte	f102d8a4b4	Extend to allow full-[byte/word/dword] writes, in LSB or MSB order.	2021-11-06 12:01:32 -07:00
Thomas Harte	25996ce180	Further doubles down on construction syntax for type conversions.	2020-05-09 23:00:39 -04:00
Thomas Harte	e3abbc9966	Renames what didn't end up being a whole SerialPort.	2019-11-09 15:21:51 -05:00