920 Commits

Author	SHA1	Message	Date
Thomas Harte	8e7340860e	Minor thematic rearrangement.	2022-05-09 16:35:17 -04:00
Thomas Harte	2ca1eb4cf8	Move set_pc into the operation-specific group.	2022-05-09 16:20:15 -04:00
Thomas Harte	0af8660181	Remove add_pc and decline_branch in favour of operation-specific signals.	2022-05-09 16:19:25 -04:00
Thomas Harte	2f7cff84d9	Enable missing rotates and shifts.	2022-05-09 11:26:01 -04:00
Thomas Harte	8e5650fde9	Clean up Instruction.hpp.	2022-05-09 10:13:42 -04:00
Thomas Harte	539932dc56	Provide function codes. TODO: optionally.	2022-05-09 09:18:02 -04:00
Thomas Harte	e35de357fa	Route reads and writes through a common path.	2022-05-08 17:17:46 -04:00
Thomas Harte	0818fd7828	Ensure no status updates fall through the cracks.	2022-05-07 21:29:12 -04:00
Thomas Harte	98cb9cc1eb	Fix CHK operand size.	2022-05-07 21:16:44 -04:00
Thomas Harte	bf8c97abbb	Permit TRAP, TRAPV and CHK to push the next PC rather than the current.	2022-05-07 20:32:39 -04:00
Thomas Harte	ad6cf5e401	Pull out magic constant, simplify sp and TAS.	2022-05-07 20:20:24 -04:00
Thomas Harte	2b3900fd14	Fix LINK A7.	2022-05-07 08:15:26 -04:00
Thomas Harte	1defeca1ad	Implement RTS, RTR, RTE.	2022-05-06 12:30:49 -04:00
Thomas Harte	ac6a9ab631	Fix TAS Dn.	2022-05-06 12:23:04 -04:00
Thomas Harte	8176bb6f79	Expose issues with TST and TAS.	2022-05-06 12:18:56 -04:00
Thomas Harte	9c266d4316	Proceed to unimplemented TST.	2022-05-06 11:33:57 -04:00
Thomas Harte	190a351a29	Fix address writeback.	2022-05-06 09:56:01 -04:00
Thomas Harte	607ddd2f78	Preserve MOVEM order in Operation.	2022-05-06 09:45:06 -04:00
Thomas Harte	fed79a116f	Be overt about the size being described here.	2022-05-06 09:22:38 -04:00
Thomas Harte	5db0ea0236	Add note for my tomorrow self.	2022-05-05 21:11:02 -04:00
Thomas Harte	06fe320cc0	Correct source counting, but this leaves the operands still being the wrong way around.	2022-05-05 21:06:53 -04:00
Thomas Harte	f7991e18de	Makes a failed attempt to implement MOVEM to registers.	2022-05-05 20:32:21 -04:00
Thomas Harte	d7d0a5c15e	Implement MOVEM to memory.	2022-05-05 18:51:29 -04:00
Thomas Harte	47f4bbeec6	Switch to a contiguous block of 16 registers.	2022-05-05 15:31:59 -04:00
Thomas Harte	9ab70b340c	Route MOVEM appropriately.	2022-05-05 12:42:57 -04:00
Thomas Harte	70cdc2ca9f	Fix MOVEP to register. ... Advance to lack of MOVEM.	2022-05-05 12:37:47 -04:00
Thomas Harte	f63a872387	BTST does not write back.	2022-05-05 12:32:15 -04:00
Thomas Harte	67462c2f92	Rewire MOVEP.	2022-05-05 12:27:36 -04:00
Thomas Harte	4a4e786060	Hit a realisation: write-back isn't going to work with MOVEP as formulated.	2022-05-05 09:26:26 -04:00
Thomas Harte	665f2d4c00	Attempts MOVEP.	2022-05-05 09:00:33 -04:00
Thomas Harte	64586ca7ba	Implement BTST/etc.	2022-05-04 20:57:22 -04:00
Thomas Harte	15c90e546f	Fix rotates and shifts to memory.	2022-05-04 19:44:59 -04:00
Thomas Harte	5aabe01b6d	Mostly fix LINK and UNLK.	2022-05-04 08:41:55 -04:00
Thomas Harte	5d1d94848c	Take a bash at LINK and UNLK.	2022-05-04 08:26:11 -04:00
Thomas Harte	7d10976e08	Add LINK and UNLINK to operand_flags.	2022-05-03 20:51:02 -04:00
Thomas Harte	d3b55a74a5	Fix LEA, proceed to non-functional LINK and UNLK.	2022-05-03 20:45:36 -04:00
Thomas Harte	de58ec71fd	Fix EXT, SWAP.	2022-05-03 20:17:36 -04:00
Thomas Harte	052ba80fd7	Add enough wiring to complete but fail EXT and JMP/JSR.	2022-05-03 15:49:55 -04:00
Thomas Harte	39f0ec7536	Get far enough through CHK to realise that MOVEM probably needs to be divided by direction.	2022-05-03 15:40:04 -04:00
Thomas Harte	af973138df	Correct decoding of Bcc.b, satisfying Bcc and BSR tests.	2022-05-03 15:32:54 -04:00
Thomas Harte	5a87506f3d	Fix Bcc, making decision that add_pc is relative to start of instruction.	2022-05-03 15:21:42 -04:00
Thomas Harte	90f0005cf2	Proceed to failing Bcc and flagging up my lack of an implementation for BSR.	2022-05-03 14:45:49 -04:00
Thomas Harte	d8b3748d24	Fix Scc size, DBcc behaviour.	2022-05-03 14:40:51 -04:00
Thomas Harte	1b224c961e	Fix Scc, add operand flags for DBcc.	2022-05-03 14:23:57 -04:00
Thomas Harte	b6ffff5bbd	Distinguish [ADD/SUB]QA from [ADD/SUB]Q.	2022-05-03 14:17:26 -04:00
Thomas Harte	b3cf13775b	Consume operand_flags into Instruction.hpp.	2022-05-03 11:09:57 -04:00
Thomas Harte	c61809f0c4	Add CMPAl.	2022-05-03 09:20:02 -04:00
Thomas Harte	2f2d6bc08b	Correct CMPw.	2022-05-03 09:05:34 -04:00
Thomas Harte	1bb809098c	Switch — messily — to a more compact way of indicating sequence.	2022-05-03 09:04:54 -04:00
Thomas Harte	011506f00d	Add basic exceptions.	2022-05-02 21:27:58 -04:00
Thomas Harte	25ab478461	Fix immediate byte and word fetches.	2022-05-02 20:17:44 -04:00
Thomas Harte	fc9a35dd04	Test add/sub, add an exception for invalid Sequences.	2022-05-02 20:09:38 -04:00
Thomas Harte	7efe30f34c	Fix (d8, _, Xn) calculation.	2022-05-02 15:09:59 -04:00
Thomas Harte	3827ecd6d3	Proceed to complete test running.	2022-05-02 12:57:45 -04:00
Thomas Harte	14532867a4	Sneaks towards testing EXT.	2022-05-02 08:00:56 -04:00
Thomas Harte	73f340586d	Proceed to building, but failing tests.	2022-05-02 07:45:07 -04:00
Thomas Harte	56fe00c5fb	Correct errors preparatory to Executor's lack of flow controller actions.	2022-05-01 20:40:57 -04:00
Thomas Harte	3c26177239	Provide both compile- and run-time operation selection options.	2022-05-01 17:39:56 -04:00
Thomas Harte	fe8f0d960d	Equivocate. ... (Specifically: addresses cannot generally be obtained in advance, as they are often the product of registers, but things like displacements, immediate values and absolute addresses can)	2022-05-01 15:30:03 -04:00
Thomas Harte	c72caef4fd	Correct further size specifiers.	2022-05-01 15:21:58 -04:00
Thomas Harte	0720a391e8	Correct address register mutations.	2022-05-01 15:18:06 -04:00
Thomas Harte	d16ac70a50	Correct include path.	2022-05-01 15:14:12 -04:00
Thomas Harte	fc8e020436	Improve field name.	2022-05-01 15:12:13 -04:00
Thomas Harte	6b073c6067	Attempt to round out addressing modes, shift to a header, as per templating on BusHandler.	2022-05-01 15:10:54 -04:00
Thomas Harte	0b19bbff8d	Marginally refactor, to avoid repetition of read/write branch.	2022-05-01 13:09:28 -04:00
Thomas Harte	42927c1e32	Establish more of the 680x0 executor loop.	2022-05-01 13:00:20 -04:00
Thomas Harte	df999978f1	Figure out what the call to perform should look like. ... Albeit that this class doesn't currently offer any of the proper flow control actions.	2022-04-30 20:34:44 -04:00
Thomas Harte	43cd740a7b	Shuffle Step to give meaning to the LSB.	2022-04-30 20:33:35 -04:00
Thomas Harte	52f355db24	Decision: operation is not a template parameter. Hence can use condition as fully typed.	2022-04-30 14:08:51 -04:00
Thomas Harte	a86c5ccdc9	Merge branch '68000Perform' of github.com:TomHarte/CLK into 68000Perform	2022-04-30 14:02:23 -04:00
Thomas Harte	e532562108	Merge branch 'master' into 68000Perform	2022-04-30 14:02:17 -04:00
Thomas Harte	8d24c00df2	Include decoded condition in Preinstruction.	2022-04-30 09:00:47 -04:00
Thomas Harte	f4074e0bba	Add basic status.	2022-04-30 08:38:28 -04:00
Thomas Harte	e4426dc952	Introduce calculate EA steps.	2022-04-29 20:30:48 -04:00
Thomas Harte	9359f6477b	Start drafting an Executor.	2022-04-29 17:12:06 -04:00
Thomas Harte	a103f30d51	Attempt to game out LEA, PEA. Add various special MOVEs.	2022-04-29 14:43:58 -04:00
Thomas Harte	78b60dbd1a	Evict MOVEM and MOVEP, enable TRAP and TRAPV, complete CHK.	2022-04-29 14:43:30 -04:00
Thomas Harte	cde75a1c00	Make steps more visible.	2022-04-29 11:26:39 -04:00
Thomas Harte	b9d243552c	MOVEs don't read from operand 2.	2022-04-29 11:22:06 -04:00
Thomas Harte	85242ba896	Add to Xcode project, template on Model as per CLR being odd. Fill in some obvious answers.	2022-04-29 11:10:14 -04:00
Thomas Harte	d16dab6f62	Starts introducing a sequencer, to resolve responsibility of perform.	2022-04-29 10:40:19 -04:00
Thomas Harte	8066b19f93	Correct typos.	2022-04-29 07:57:02 -04:00
Thomas Harte	abd2a831a3	Added a further ambiguity.	2022-04-29 05:08:44 -04:00
Thomas Harte	824d3ae3f7	Conclusion: a union does produce better code. ... (But needn't be so verbose)	2022-04-29 04:51:02 -04:00
Thomas Harte	727a14c6f9	Add notes for myself on decisions yet to make.	2022-04-29 03:53:17 -04:00
Thomas Harte	13d20137d3	Tackle two lingering references to exception_handler.	2022-04-29 03:38:23 -04:00
Thomas Harte	9680566595	Include in automated build, temporarily.	2022-04-28 20:42:44 -04:00
Thomas Harte	33c9ea2cf7	A flow controller feels more natural than an exception handler.	2022-04-28 20:42:04 -04:00
Thomas Harte	1d8d2b373b	Port all simple instruction bodies.	2022-04-28 16:55:47 -04:00
Thomas Harte	611b472b12	Add evaluate_condition, to check standard 68000 condition codes.	2022-04-28 16:54:57 -04:00
Thomas Harte	bb73eb0db3	Start working on an isolation of 68000 instruction execution.	2022-04-28 15:35:40 -04:00
Thomas Harte	39261436c8	Remove unused type alias.	2022-04-27 19:53:32 -04:00
Thomas Harte	5e355383df	Correct SIB test.	2022-04-27 19:53:15 -04:00
Thomas Harte	9cbbb6e508	Adjust path to match namespace; add to Qt project.	2022-04-27 08:05:36 -04:00
Thomas Harte	8902bb1af0	Include size and supervisor flag in Preinstruction.	2022-04-26 19:44:02 -04:00
Thomas Harte	baf1bd354d	Avoid packing/unpacking of operands.	2022-04-26 19:37:07 -04:00
Thomas Harte	539c2985aa	Fill in size table, define quick to return a uint32_t.	2022-04-26 12:30:14 -04:00
Thomas Harte	5c356e15b5	Completes requires_supervisor.	2022-04-25 20:05:45 -04:00
Thomas Harte	8ff0b71b29	Subsume MOVEQ into MOVE.l; add missing invalid_operands.	2022-04-25 19:58:19 -04:00
Thomas Harte	8f8f201186	Complete transition to simple AND-based verification.	2022-04-25 16:23:16 -04:00
Thomas Harte	0c688757b0	Adapt the last of the MOVEs, TAS, NOT, SUB and TST.	2022-04-25 16:05:44 -04:00
Thomas Harte	5778e92e70	Adapt MOVE, DIV, MUL, OR.	2022-04-25 15:43:25 -04:00
Thomas Harte	3268ea42ff	Translate SUB, PEA.	2022-04-25 12:41:41 -04:00
Thomas Harte	1538500903	Add enough to make AND masks the default case.	2022-04-25 12:30:44 -04:00
Thomas Harte	6ca30a16ca	Update JMP, JSR.	2022-04-25 12:05:07 -04:00
Thomas Harte	e6dc2e0d31	Add EXG, EXT.	2022-04-25 11:49:14 -04:00
Thomas Harte	9bbd1390c1	Add new-style validation of EORI to CCR, move EXG decoding into page navigation.	2022-04-25 11:43:30 -04:00
Thomas Harte	27f8db6e8b	Update DBcc, DIVU/DIVS, EOR.	2022-04-25 09:49:18 -04:00
Thomas Harte	dda0c0e097	Update CMPM, CMPI.	2022-04-25 09:39:22 -04:00
Thomas Harte	f5ea5c26a3	Translate CHK, CLR, CMP, CMPA.	2022-04-24 21:05:00 -04:00
Thomas Harte	d01fa96177	Port BSR, BTST.	2022-04-24 20:49:41 -04:00
Thomas Harte	03caa53863	Translate BSET.	2022-04-24 19:58:10 -04:00
Thomas Harte	4f4a2e6d92	Translate ASL, ASR, Bcc, BCHG, BCLR.	2022-04-24 19:53:54 -04:00
Thomas Harte	87178ed725	Port AND.	2022-04-24 15:12:18 -04:00
Thomas Harte	94e5436f6e	Attempt a more compact retelling.	2022-04-24 14:47:14 -04:00
Thomas Harte	b965f2053a	Start experimenting with a simple AND for operand validation.	2022-04-24 10:43:06 -04:00
Thomas Harte	edee078f0a	Eliminate last set of failures.	2022-04-22 20:57:45 -04:00
Thomas Harte	d4b766bf3f	Introduce directional ADD/SUB/AND/OR. ... Just 512 failures to go.	2022-04-22 20:37:09 -04:00
Thomas Harte	72772c9a83	Remove branch from combined_mode. ... On x86 it was probably only a conditional move, but this is fine.	2022-04-22 15:11:41 -04:00
Thomas Harte	4c806d7c51	Tidy up slightly, ahead of a final push to getting complete test success. ... After which I can start undoing style errors.	2022-04-22 14:51:25 -04:00
Thomas Harte	96afcb7a43	Introduce remainder of tests.	2022-04-22 14:33:43 -04:00
Thomas Harte	efeee5160e	Add tests for RTE, RTR, TRAP, TRAPV, CHK.	2022-04-22 10:06:39 -04:00
Thomas Harte	06fb502047	Add MUL/DIV tests and exclusions.	2022-04-22 09:47:16 -04:00
Thomas Harte	977192f480	Resolve D-page decoding errors. ... In particular: that I'd overlooked CMPM, and was treating NOT as two-operand.	2022-04-22 09:24:16 -04:00
Thomas Harte	cf66d9d38d	Add failing tests for EOR, NOT, OR; disambiguate EOR vs CMP.	2022-04-21 20:36:04 -04:00
Thomas Harte	25eeff8fc5	Correct CMP decoding, correct AND as far as asymmetry of Dn, Dn.	2022-04-21 20:14:52 -04:00
Thomas Harte	bf9fc0ae96	Correct decoding of BSR.	2022-04-21 16:24:34 -04:00
Thomas Harte	a8a1a74b79	Correct BSRb quick value.	2022-04-21 16:13:06 -04:00
Thomas Harte	549e440f7c	Add 'quick' decoding and testing.	2022-04-21 16:05:00 -04:00
Thomas Harte	45c02c31f8	Add MOVEM exclusions.	2022-04-21 15:47:34 -04:00
Thomas Harte	b6b092d124	Add tests, exclusions for rest of shift/roll group.	2022-04-21 11:26:56 -04:00
Thomas Harte	3af93ada6f	Test and correct Bcc, BSR, CLR, NEGX, NEG.	2022-04-20 20:19:56 -04:00
Thomas Harte	dc16928f74	Add appropriate exclusions for JSR, JMP, Scc.	2022-04-20 16:56:26 -04:00
Thomas Harte	80ff146620	Add CMP, CMPA and TST tests and exclusions.	2022-04-20 16:29:45 -04:00
Thomas Harte	d4fe9d8166	Complete BTST/etc exclusions.	2022-04-20 16:16:24 -04:00
Thomas Harte	85a0af03c1	Import more standard JSON; start validating.	2022-04-20 09:17:00 -04:00
Thomas Harte	dc43f5605b	Give MOVEPs precedence.	2022-04-20 08:40:56 -04:00
Thomas Harte	fab064641f	Add Move[to/from][SR/CCR/USP] tests, correct decodings.	2022-04-20 07:59:13 -04:00
Thomas Harte	316e9681cc	Weed out false PEAs.	2022-04-19 20:34:08 -04:00
Thomas Harte	4181313cc6	Correct decoding of SWAP.	2022-04-19 20:28:00 -04:00
Thomas Harte	6aabc5e7b0	Test LEA, PEA, add name for MOVEq.	2022-04-19 19:45:51 -04:00
Thomas Harte	343a8e0192	Resolve wrong-headed mapping of LEA to MOVEAl.	2022-04-19 19:36:21 -04:00
Thomas Harte	ef87d09cfa	Clear up MOVEs, fail on MOVEAs.	2022-04-19 17:13:23 -04:00
Thomas Harte	d21c67f237	Don't permit byte move from address register.	2022-04-19 16:49:26 -04:00
Thomas Harte	de40fed248	Test MOVEs and add operand validation.	2022-04-19 16:31:03 -04:00
Thomas Harte	76d7e0e1f8	Test and correct SUBs.	2022-04-19 16:27:20 -04:00
Thomas Harte	1f585d67b6	ADDA: correct decoding, add validation.	2022-04-19 14:43:01 -04:00
Thomas Harte	5b22e94a4b	Map invalid reg+mode combinations to AddressingMode::None; add validation of ADDs and decoding of ADDX.	2022-04-19 14:36:36 -04:00
Thomas Harte	7749aef6b6	Improve const correctness.	2022-04-19 14:35:40 -04:00
Thomas Harte	5de8fb0d08	Disallow four illegal NBCD addressing modes.	2022-04-19 09:59:02 -04:00
Thomas Harte	19f7335926	Add post validation step.	2022-04-19 09:44:02 -04:00
Thomas Harte	99f4cd867d	Decode the two EXTs.	2022-04-19 08:42:17 -04:00
Thomas Harte	93fe3459fd	The quick value won't always fit in reg; turf the problem elsewhere.	2022-04-19 08:37:35 -04:00
Thomas Harte	1abd3bd7f3	Decode SWAP.	2022-04-19 08:37:13 -04:00
Thomas Harte	fc4fd41be4	Reorder from most specific to least.	2022-04-19 08:00:52 -04:00
Thomas Harte	e4c6251ef5	Express the BSR/Bcc.l test properly.	2022-04-18 14:42:31 -04:00
Thomas Harte	7aa250eaf7	Advances to hitting the same absent/present mapping as the old decoder.	2022-04-18 14:41:26 -04:00
Thomas Harte	ff380b686a	Decode MOVEq.	2022-04-18 09:12:45 -04:00
Thomas Harte	d2452f4b68	Fix SUBQ ExtendedOperation mappings.	2022-04-18 09:08:49 -04:00
Thomas Harte	deb9c32a38	Add missing Sccs.	2022-04-18 09:04:17 -04:00
Thomas Harte	440f45b996	Attempt decoding and disambiguation of Scc, DBcc, Bcc and BSR.	2022-04-18 08:55:46 -04:00
Thomas Harte	7d64c4ec66	Add STOP.	2022-04-18 08:29:10 -04:00
Thomas Harte	7fe0d530c1	Add a decoder for TRAP.	2022-04-18 08:05:33 -04:00
Thomas Harte	c944767554	Better document decoding patterns, add LEA and CHK.	2022-04-18 08:00:43 -04:00
Thomas Harte	fde5a1c507	Ensure ADDI, SUBI, etc, provide an operation.	2022-04-18 07:42:30 -04:00
Thomas Harte	1991ed0804	Introduce failing [partial-]test of new 68000 decoder.	2022-04-18 07:23:25 -04:00
Thomas Harte	4eb752b000	Even out tabs.	2022-04-15 20:41:39 -04:00
Thomas Harte	bfb29a58f3	Take another crack at neatness; make LEA overt.	2022-04-15 20:33:59 -04:00
Thomas Harte	f86e455a87	Advance permissively through the 4xxx page to LEA.	2022-04-15 16:01:33 -04:00
Thomas Harte	faa35fe9fc	Decode MOVE and the fixed 0x4xxx set.	2022-04-15 15:40:31 -04:00
Thomas Harte	89b8b59658	Ostensibly completes the 0 line.	2022-04-15 15:33:54 -04:00
Thomas Harte	de55a1adc4	Require a model for decoding; shift a bunch of immediates into ExtendedOperation.	2022-04-15 09:40:37 -04:00
Thomas Harte	d1613025ee	For now, assume the .q actions can be handled inside Preinstruction.	2022-04-13 09:29:12 -04:00
Thomas Harte	cc4431c409	Expand decode to accept a wider array of operations, and then funnel them down.	2022-04-12 16:17:30 -04:00
Thomas Harte	3d5986c55d	Some minor style changes, plus I think I've talked myself into an expanded Operation-tracking enum. Probably.	2022-04-12 14:54:11 -04:00
Thomas Harte	9aeb6ee532	Formally prepare for one- and two-operand instructions.	2022-04-12 09:14:46 -04:00
Thomas Harte	e7f6cc598d	Make first attempt to complete broad phase of decoding.	2022-04-12 09:08:46 -04:00
Thomas Harte	cd465dd121	Decode page E.	2022-04-12 09:04:40 -04:00
Thomas Harte	174b48a14a	Populate lines 9 and D.	2022-04-12 08:57:40 -04:00
Thomas Harte	bca18e7aba	Fill in line decoders for 5, 6 and 7. ... This leaves 9, D and E to go.	2022-04-12 08:44:32 -04:00
Thomas Harte	17e761d6c6	Add enough code to pages 0–3 to shift problem to decode().	2022-04-12 08:36:44 -04:00
Thomas Harte	c50556dde4	Create empty line decoders.	2022-04-12 08:16:29 -04:00
Thomas Harte	dd5bdd67d7	Add B page and a large chunk of 4.	2022-04-12 07:49:08 -04:00
Thomas Harte	21ac9363e9	Add page 8.	2022-04-11 16:32:57 -04:00
Thomas Harte	8e3cccf4d6	Begins a formalised 68k decoder.	2022-04-11 15:00:55 -04:00
Thomas Harte	bb5cf570e5	Remove conditional, make generic enough for both 32- and 64-bit operation.	2022-04-10 15:18:23 -04:00
Thomas Harte	7002d6d306	Improve accuracy of comment.	2022-04-10 09:37:18 -04:00
Thomas Harte	1b8d8f3a04	Default to 32-bit versions.	2022-04-10 09:35:58 -04:00
Thomas Harte	284440336d	Correct rotate_mask().	2022-04-10 09:31:39 -04:00
Thomas Harte	140ae7a513	Clarify template parameters.	2022-04-10 08:57:09 -04:00
Thomas Harte	7de50b5e2e	Provide 64-bit me, mb and sh. Add direct getter for rotate masks.	2022-04-09 21:08:01 -04:00
Thomas Harte	4652a84b43	Add exposition.	2022-04-09 19:20:13 -04:00
Thomas Harte	9e0755bc86	Introduce overlooked: ld, ldu, rldclx, rldcrx, rldicx, rldiclx, rldicrx, rldimix.	2022-04-09 18:28:51 -04:00
Thomas Harte	da0f7d7907	Rearrange into alphabetical order.	2022-04-09 10:20:03 -04:00
Thomas Harte	88d72bf31d	Fill in more mnemonics.	2022-04-08 10:01:52 -04:00
Thomas Harte	aac2f7dd73	Add missing validations.	2022-04-08 09:47:04 -04:00
Thomas Harte	1f44ad1723	Completes test cases.	2022-04-06 21:09:58 -04:00
Thomas Harte	4ab1857a11	Complete MPC601 commentary.	2022-04-06 20:53:44 -04:00
Thomas Harte	d23c714ec7	Build in an optional post hoc validation. ... TODO: validate.	2022-04-05 11:23:54 -04:00
Thomas Harte	59a1fde2a1	Fix is_zero_mask.	2022-04-03 20:37:09 -04:00
Thomas Harte	31276de5c3	Complete 'misc instructions' tests.	2022-04-03 20:33:32 -04:00
Thomas Harte	c581aef11d	Test as far as mffs.	2022-04-03 18:29:40 -04:00
Thomas Harte	7f6a955a71	Complete the cmp set.	2022-04-03 15:50:03 -04:00
Thomas Harte	125d97cc41	Complete floating point tests.	2022-04-03 08:55:28 -04:00
Thomas Harte	de7d9ba471	Add further floating point tests.	2022-04-03 08:06:59 -04:00
Thomas Harte	ad54b44235	Begin documentation and testing of the floating point instructions.	2022-04-02 19:58:21 -04:00
Thomas Harte	42532ec0f5	Test floating point loads and stores.	2022-04-02 15:40:17 -04:00
Thomas Harte	b84fa619da	Test integer loads and stores.	2022-04-02 15:27:12 -04:00
Thomas Harte	8a1409184f	Add decoding of lwa.	2022-04-02 10:31:55 -04:00
Thomas Harte	8a3c16a5bc	Add lwa.	2022-04-02 10:26:47 -04:00
Thomas Harte	6343c65ce2	Document further; mftb is optional.	2022-04-02 10:09:58 -04:00
Thomas Harte	d5967f7834	Correct decoding of stwcx. and stdcx.	2022-04-01 20:37:36 -04:00
Thomas Harte	d5f7650ac1	Test synchronising loads and stores, further expand documentation.	2022-04-01 18:30:48 -04:00
Thomas Harte	8f580c256c	Remove explanations; saying nothing is better than giving incomplete advice.	2022-04-01 17:49:34 -04:00
Thomas Harte	7c8f044380	Complete shift tests.	2022-04-01 17:22:32 -04:00
Thomas Harte	8efd506471	Transcribe up to the end of 'e', use extswx and remove extsw.	2022-04-01 17:11:57 -04:00
Thomas Harte	e83267751e	Start shuffling parameters into conventional order; expand on cmp–cmpli, dcbf–dcbz.	2022-03-30 20:36:46 -04:00
Thomas Harte	84f0b0a84c	Test rotates.	2022-03-30 16:43:09 -04:00
Thomas Harte	52e7226655	Merge branch 'PowerPCTests' of github.com:TomHarte/CLK into PowerPCTests	2022-03-29 20:50:40 -04:00
Thomas Harte	b89c8decd4	Test addx–divwx and mtcrf; document fields for crand, etc.	2022-03-29 20:48:43 -04:00
Thomas Harte	d783975597	Start offering a list of relevant fields per Operation.	2022-03-29 19:59:21 -04:00
Thomas Harte	5ec291df5c	Merge branch 'PowerPCTests' of github.com:TomHarte/CLK into PowerPCTests	2022-03-29 14:38:28 -04:00
Thomas Harte	0a45355055	Add a few more field comments.	2022-03-29 14:37:21 -04:00
Thomas Harte	99ad40f3e0	Test subfcx, subfx; correct decoding of oe().	2022-03-28 20:39:52 -04:00
Thomas Harte	b9c8016aca	Merge branch 'PowerPCTests' of github.com:TomHarte/CLK into PowerPCTests	2022-03-28 20:20:59 -04:00
Thomas Harte	8ad1f2d4f5	Add bad attempt to catch subfc.	2022-03-28 20:18:41 -04:00
Thomas Harte	dc30581be0	Fix typo; . -> ,	2022-03-28 16:39:55 -04:00
Thomas Harte	2e56b606fa	Improve file division, document some further operations.	2022-03-27 18:44:56 -04:00
Thomas Harte	d84c72afe5	Test loads and stores, and immediate arithmetic.	2022-03-27 08:47:01 -04:00
Thomas Harte	4f6a9917c6	Test lbzx, lbzux.	2022-03-26 08:45:07 -04:00
Thomas Harte	3d48183753	Test lwzux.	2022-03-25 20:31:47 -04:00
Thomas Harte	33c31eb798	Test lwzx.	2022-03-25 20:23:21 -04:00
Thomas Harte	73ae7ad82f	Resolve final branch test: aa() applies.	2022-03-25 20:10:08 -04:00
Thomas Harte	1a5d3bb69c	Match majority of branch tests.	2022-03-25 08:41:57 -04:00
Thomas Harte	7d4fe55d63	Handle bclrx set and clear.	2022-03-25 06:25:06 -04:00
Thomas Harte	089e03afe8	Navigates bcctrx tests, adding simplified bo() helpers and bi() helpers.	2022-03-24 20:44:03 -04:00
Thomas Harte	8e019f01ab	Document dozx and dozi.	2022-03-21 10:49:01 -04:00
Thomas Harte	77bdaf3c78	These are likely to be useful outside of the decoder.	2022-03-21 10:41:17 -04:00
Thomas Harte	0b6828c895	Decision: these enums will be at namespace scope.	2022-03-21 10:19:30 -04:00
Thomas Harte	d4704c656f	Merge branch 'PowerPCTests' of github.com:TomHarte/CLK into PowerPCTests	2022-03-21 10:18:36 -04:00
Thomas Harte	c01192c784	Add exposition for absx to divsx.	2022-03-21 10:17:55 -04:00
Thomas Harte	8adb611edf	Attempt to clarify with an enum.	2022-03-19 12:27:28 -04:00
Thomas Harte	e5af5b57ad	Add documentation for bx, bcx, bcctrx. ... Catch bcx tests.	2022-03-18 19:55:26 -04:00
Thomas Harte	1725894fe9	Eliminate redundant CMPSD, CDQ, CWDE. ... Also removes IBTS for now, as I'm unclear where it should sit in the opcode map.	2022-03-12 12:24:44 -05:00
Thomas Harte	fd4f85eb19	Add SMSW.	2022-03-12 12:23:48 -05:00
Thomas Harte	f1c4864016	Eliminate INSD.	2022-03-12 11:37:21 -05:00
Thomas Harte	e6bd265729	Explain which BOUNDs operand is which.	2022-03-11 20:34:28 -05:00
Thomas Harte	c22e8112e7	Expand exposition.	2022-03-11 20:30:56 -05:00
Thomas Harte	44252984c2	Eliminate INT3 special case.	2022-03-11 14:03:46 -05:00
Thomas Harte	4b4f92780e	Shuffle extension word order. ... The primary objective here is simplifying index calculation, but as per the note it does also potentially open up options with regard to packing in the future.	2022-03-11 13:24:45 -05:00
Thomas Harte	f694620087	Resolve TODO.	2022-03-11 13:10:44 -05:00
Thomas Harte	9b4048ec6e	The address size modifier doesn't seem to affect far address sizes. ... It's meant to affect only instructions with operands that reside in memory, I think. So probably only ::DirectAddress in my nomenclature. More research to do.	2022-03-11 12:46:07 -05:00
Thomas Harte	c744a97e3c	Ensure no extensions for default constructed Instruction.	2022-03-11 11:55:26 -05:00
Thomas Harte	91d75d7704	Switch strategy on 8086 instruction lengths.	2022-03-11 09:48:26 -05:00
Thomas Harte	dc8cff364f	Switch to common test.	2022-03-11 09:48:02 -05:00
Thomas Harte	572dc40e6b	Allow assignments.	2022-03-11 09:47:23 -05:00
Thomas Harte	f92ffddb82	Add instruction length limits.	2022-03-10 20:47:56 -05:00
Thomas Harte	641e0c1afc	Resolve default segment question.	2022-03-10 20:27:35 -05:00
Thomas Harte	bf7faa80c1	Add TODO.	2022-03-10 16:47:54 -05:00
Thomas Harte	a2ae3771eb	Add test for switch to Source::IndirectNoBase.	2022-03-10 15:45:56 -05:00
Thomas Harte	673ffc50da	Switch to intended compact version of Instruction.	2022-03-10 15:14:50 -05:00
Thomas Harte	6dc9973754	Incorporate length into Instruction.	2022-03-10 07:12:12 -05:00
Thomas Harte	cf6a910630	Handle no-base case directly in existing switch.	2022-03-09 20:20:32 -05:00
Thomas Harte	520baa6ec8	Formalise IndirectNoBase and permit a knowledgable caller to avoid conditionals.	2022-03-09 20:19:40 -05:00
Thomas Harte	bbf925a27e	Clarify, unify and correct decoding and encoding of [CALL/RET/JMP][near/far/relative/absolute].	2022-03-09 16:48:06 -05:00
Thomas Harte	381fd5dbe4	E8 is a relative call.	2022-03-09 16:37:07 -05:00
Thomas Harte	ead8b7437e	Remove done TODO.	2022-03-09 15:26:20 -05:00
Thomas Harte	acd9df6745	Fix segment/offset sizes for far calls.	2022-03-09 15:23:43 -05:00
Thomas Harte	f96c051932	Record PUSH immediate operation size.	2022-03-09 14:24:57 -05:00
Thomas Harte	67b2e40fae	Fixed: INs and OUTs remain single byte.	2022-03-09 10:51:16 -05:00
Thomas Harte	081a2acd61	Fix shift group operand size.	2022-03-09 09:33:25 -05:00
Thomas Harte	de79acc790	Fix RegAddr/AddrRegs and group 2 decoding.	2022-03-09 08:38:34 -05:00
Thomas Harte	21d4838322	Fix current implementation of data_segment. ... As far as it goes.	2022-03-08 17:08:21 -05:00
Thomas Harte	926a373591	Extend SIB test, correct decoder.	2022-03-08 15:03:37 -05:00
Thomas Harte	a954f23642	Attempt 32-bit modregrm + SIB parsing.	2022-03-08 14:39:49 -05:00
Thomas Harte	41a104cc10	Adds special test/control/debug MOVs. ... This'll do; it's not ideal but avoids bloating up the `Source` enum.	2022-03-07 17:04:05 -05:00
Thomas Harte	f0b4971c7b	Correct SHLD format.	2022-03-07 16:39:02 -05:00
Thomas Harte	8e669a32a3	Take a stab at group 8.	2022-03-07 16:34:56 -05:00
Thomas Harte	0e16e7935e	Correct double reference to Group 6.	2022-03-07 16:26:17 -05:00
Thomas Harte	7ea84d9a4e	Add MOVZX, MOVSX.	2022-03-07 16:25:44 -05:00
Thomas Harte	7313c89dec	Add BT, BTS, BTR, BTC, BSF, BSR.	2022-03-07 16:23:25 -05:00
Thomas Harte	35a66c03c2	Add the SETs.	2022-03-07 10:32:34 -05:00
Thomas Harte	bbb3168bae	Adds the missing shift group segues at c0 and c1.	2022-03-07 09:18:59 -05:00
Thomas Harte	1ea9d3faf8	Introduce additional forms of IMUL.	2022-03-07 09:05:22 -05:00
Thomas Harte	4479be4fd0	Add the two immediate PUSHes.	2022-03-06 14:28:41 -05:00
Thomas Harte	91a6bf671d	Also 'easy': LSS, LFS, LGS. ... Though perhaps I'm off on LES and LDS?	2022-03-06 09:28:43 -05:00
Thomas Harte	49b5889d9e	0x8c is available on the 8086.	2022-03-06 09:24:59 -05:00
Thomas Harte	ede61ae130	Flag up TODOs, for easier in-editor navigation.	2022-03-05 17:48:01 -05:00
Thomas Harte	7a79111767	Add the easiest 80386 extensions: PUSH/POP FS/GS and longer conditional jumps.	2022-03-05 17:32:21 -05:00
Thomas Harte	6432521b9d	Correct two references to JP that should be JL.	2022-03-05 17:16:32 -05:00
Thomas Harte	65f578fe61	Add notes on all missing opcodes.	2022-03-05 17:16:13 -05:00
Thomas Harte	3a8eb4a4f0	Add 80386 segment overrides.	2022-03-05 17:03:46 -05:00
Thomas Harte	eb180656bb	Fix $8e data size, add $8c.	2022-03-05 17:00:48 -05:00
Thomas Harte	1afcbba218	Clarify sign extension availability.	2022-03-05 16:44:26 -05:00
Thomas Harte	8a0902a83b	Adapts existing opcodes for 32-bit parsing.	2022-03-05 13:52:07 -05:00
Thomas Harte	dfb312fee6	Make column and row meanings overt.	2022-03-05 11:56:08 -05:00
Thomas Harte	11bb594fa2	Sets up [ignored] memory and data size prefixes.	2022-03-02 20:23:35 -05:00
Thomas Harte	8e3ae2c78f	Add opcode map as documentation.	2022-03-02 20:00:21 -05:00
Thomas Harte	4b4135e35a	Correct #undef.	2022-03-01 18:23:24 -05:00
Thomas Harte	d1148c4cab	Switch to constexpr function, for guaranteed semantics.	2022-03-01 17:30:41 -05:00
Thomas Harte	8ee62b4789	Simplify address size semantics. ... Since it'll no longer be a mode-dependant toggle, but a fully-retained value.	2022-03-01 17:29:26 -05:00
Thomas Harte	5e7a142ff1	Fix is_write errors, update comment, add additional source for asserts.	2022-03-01 16:51:54 -05:00
Thomas Harte	2c816db45e	Refactor: (i) to expose effective address calculation; and (ii) to include address size in Instruction.	2022-03-01 09:36:37 -05:00
Thomas Harte	b920507f34	Double down on AddressT, add an assert on memory_mask.	2022-02-28 10:03:58 -05:00
Thomas Harte	afbc57cc0c	Incorporate displacement, switch macro flag.	2022-02-28 09:53:23 -05:00
Thomas Harte	9f12c009d6	Correct data size when accessing address registers.	2022-02-27 19:45:03 -05:00
Thomas Harte	84ac68a58b	Fix indirect memory read/write	2022-02-27 18:43:00 -05:00
Thomas Harte	27d1df4699	Introduce enough of a DataPointerResolver test to build but fail.	2022-02-27 18:27:58 -05:00
Thomas Harte	0d7a7dc7c9	Introduce DataPointerResolver, to codify the meaning of DataPointer and validate that enough information is present.	2022-02-27 11:25:02 -05:00
Thomas Harte	b8bff0e7f5	Double up eSP, eBP, eSI, eDI and AH, CH, DH, BH enums, as per Intel's encoding.	2022-02-24 05:16:15 -05:00
Thomas Harte	60bf1ef7ea	Rename SourceSIB to DataPointer, extend to allow for an absent base.	2022-02-23 08:28:20 -05:00
Thomas Harte	95976d8b58	Add missing #include.	2022-02-21 16:33:58 -05:00
Thomas Harte	ecb20cc29b	Improve tabbing.	2022-02-21 16:09:03 -05:00
Thomas Harte	b6183e86eb	Clarifies model tests by macro; adds the address size toggle.	2022-02-21 16:06:02 -05:00
Thomas Harte	229af0380c	This is normatively called the address size.	2022-02-21 15:52:16 -05:00
Thomas Harte	b968a662d3	Dump notes on intended Instruction layout, add memory size flag.	2022-02-21 15:48:58 -05:00
Thomas Harte	159e869fe6	Justifies the templatisation.	2022-02-21 15:33:08 -05:00
Thomas Harte	76814588b8	Template Instruction on its content size.	2022-02-21 12:36:03 -05:00
Thomas Harte	1934c7faa2	Switch Decoder into a template.	2022-02-21 12:21:57 -05:00
Thomas Harte	9e9e160c43	Eliminate Ind[BXPlusSI/etc] in favour of specifying everything via a ScaleIndexBase.	2022-02-21 11:45:46 -05:00
Thomas Harte	546b4edbf1	Ensure ScaleIndexBase can be used constexpr; add note-to-self on indexing table.	2022-02-20 19:22:28 -05:00
Thomas Harte	63d8a88e2f	Switch to holding the SIB as a typed ScaleIndexBase. ... (and permit copy assignment)	2022-02-20 17:54:53 -05:00
Thomas Harte	75d2d64e7c	Albeit that it requires nuanced shift/roll semantics, eliminates CL constant. ... Shifts and rolls are already slightly semantically special for being undefined for values greater than 8/16/32 — i.e. in some implementations they don't even use the entirety of CL, just the low five bits. Which makes me feel a little better. The upside of no ambiguity between eCX size 1 and CL justifies the trade.	2022-02-20 17:52:19 -05:00
Thomas Harte	a5113998e2	Accept that IN and OUT are going to have special semantics, thereby kill ::AX and ::DX.	2022-02-20 17:15:01 -05:00
Thomas Harte	4d2e8cd71d	Adds a presently-unreachable step for SIB consumption.	2022-02-19 18:00:27 -05:00
Thomas Harte	30b355fd6f	Chips away further at the legacy register names.	2022-02-18 18:37:47 -05:00
Thomas Harte	12df7112da	Starts adjusting the concept of a Source.	2022-02-17 11:32:09 -05:00
Thomas Harte	cd5ca3f65b	Attempts a full decoding of the 80286 instruction set.	2022-02-10 17:13:50 -05:00
Thomas Harte	0bd63cf00f	Introduces the easy F page instructions.	2022-02-10 09:35:05 -05:00
Thomas Harte	7ceb3369eb	Attempts decoding of the 80186 set.	2022-02-09 17:51:48 -05:00
Thomas Harte	ae21726287	Splits 80186 additions from 80286; fills in a touch more.	2022-02-01 20:38:10 -05:00
Thomas Harte	a4da1b6eb0	Begins enumerating the 80286 and 80386 instructions.	2022-01-31 09:11:06 -05:00
Thomas Harte	85bfd2eba3	Remove further errant 'Awaiting's.	2022-01-31 08:22:07 -05:00
Thomas Harte	2d543590dc	Make a noun, for better consistency.	2022-01-31 08:14:33 -05:00
Thomas Harte	2574407afb	Relocates MinIntTypeValue to Numeric.	2021-06-22 19:33:02 -04:00
Thomas Harte	135134acfd	Adds a shell for video emulation.	2021-03-18 12:47:48 -04:00
Cacodemon345	82717b39bb	Fix compilation on GCC 10	2021-03-13 01:27:29 +06:00
Thomas Harte	cbf5a79ee8	Takes a swing at improper key repeat.	2021-02-28 16:46:09 -05:00
Thomas Harte	5d1970d201	Adds a hacky different guess at how register access might work.	2021-02-19 21:46:18 -05:00
Thomas Harte	2e9065b34c	Increases number of fixed initial values.	2021-02-18 22:48:53 -05:00
Thomas Harte	2a45e7a8d4	Slows timer X, to what may or may not be correct.	2021-02-15 16:40:27 -05:00
Thomas Harte	f8f0ff0fae	Add timer X counting. ... Still no interrupts.	2021-02-15 16:29:25 -05:00
Thomas Harte	f5dcff2f29	Honours interrupt vector.	2021-02-15 15:05:56 -05:00
Thomas Harte	eccf5ca043	Makes first effort to wire up the ADB vertical blank input. ... However: looking at the disassembly, I'm not sure it really is wired to INTR. So work to do.	2021-02-14 22:20:58 -05:00
Thomas Harte	c284b34003	Resolves inability of ADB microcontroller to read its own ROM (!)	2021-02-13 17:53:40 -05:00
Thomas Harte	2c4dcf8843	Edges towards implementing an ADB device.	2021-02-12 21:50:24 -05:00
Thomas Harte	e83b2120ce	Tidies up, allows Operations and AddressingModes to be posted directly to ostreams.	2021-02-10 21:46:56 -05:00
Thomas Harte	3c7f9a43ad	Merge branch 'AppleIIgs' of github.com:TomHarte/CLK into AppleIIgs	2021-02-08 18:43:27 -05:00
Thomas Harte	82312d3b59	Provide a more convincing version of port output.	2021-02-08 18:14:08 -05:00
Thomas Harte	93a80a30d3	With correct divider appears to get reset requests posted.	2021-02-07 23:05:01 -05:00
Thomas Harte	77b1efd176	Sets sensible 'reset' values.	2021-02-07 21:53:57 -05:00
Thomas Harte	acfab1dfb3	Starts to make some effort at timers.	2021-02-06 21:02:44 -05:00
Thomas Harte	819e9039ab	Corrects printed target address for ZeroPageRelative.	2021-02-04 20:54:31 -05:00
Thomas Harte	b8c6d4b153	Rips out my high-level ADB microcontroller protocol implementation. ... Adds just enough that the main computer validates the ADB controller as present and talking.	2021-01-30 17:53:27 -05:00
Thomas Harte	5eddc92846	Implements direction registers.	2021-01-28 21:06:11 -05:00
Thomas Harte	f50e8b5106	If I'm going to maintain the max_address approach, & is 'correct'. ... % +1 would be 'more correct', but I think this approach is probably misguided.	2021-01-27 18:31:11 -05:00
Thomas Harte	dcc2fe0990	Improves M50470 entry-point detection, adds test output.	2021-01-26 21:29:17 -05:00
Thomas Harte	56111c75ae	Makes first efforts towards disassembly.	2021-01-26 19:52:30 -05:00
Thomas Harte	cc90935abd	Starts to provide just a touch of reflection.	2021-01-26 19:22:00 -05:00
Thomas Harte	413e42e1b6	Attempts to fix BBC. ... But thereby stops all ADB output.	2021-01-25 22:34:03 -05:00
Thomas Harte	fc4bda0047	Experimentally flipping interpretation of the output bit gives something closer to coherent.	2021-01-25 22:02:39 -05:00
Thomas Harte	c8beb59172	Attempts properly to track ADB bus activity. ... Output is not yet a valid ADB stream. Work to do.	2021-01-25 17:43:22 -05:00
Thomas Harte	8789ffda15	Corrects performer storage, RMW/W confusion, implicit casts, port readback.	2021-01-24 22:30:42 -05:00
Thomas Harte	e8e604dc3c	Attempts to wire up M50470 and GLU. ... Resulting in an unexpected interest in R15. Bugs to find, I guess.	2021-01-24 18:07:05 -05:00
Thomas Harte	57e0fdfadc	Ensures ADB microcontroller is clocked. ... And runs at the 'correct' speed (i.e. modulo my instruction-by-instruction implementation).	2021-01-23 22:55:12 -05:00
Thomas Harte	36aebe0ff9	Posts cycle lengths.	2021-01-23 21:58:52 -05:00
Thomas Harte	051d2b83f4	Corrects TSX lookup.	2021-01-23 15:45:21 -05:00
Thomas Harte	17b12120eb	Corrects bit-selection shifts.	2021-01-21 23:13:00 -05:00
Thomas Harte	6e9ce50569	Corrects duration-based iteration.	2021-01-21 23:05:43 -05:00
Thomas Harte	adef2e9b4e	Starts formalising end conditions.	2021-01-21 22:36:44 -05:00
Thomas Harte	0fafbf5092	Completes M50740 instruction set.	2021-01-21 19:08:38 -05:00
Thomas Harte	c10c161d39	Implements ADC and SBC.	2021-01-21 18:53:24 -05:00
Thomas Harte	04024ca159	Adds BIT.	2021-01-20 21:41:43 -05:00
Thomas Harte	64d556f60f	Implements shifts and rotates.	2021-01-20 21:39:13 -05:00
Thomas Harte	8564e7406b	Corrects index-mode CMP, LDA.	2021-01-20 21:32:46 -05:00
Thomas Harte	ebdb58d790	Seemingly advances to the first indefinite loop.	2021-01-20 21:18:52 -05:00
Thomas Harte	cf8afc70b2	Takes a swing at BBC, BBS.	2021-01-20 20:52:04 -05:00
Thomas Harte	4f02e8fbaf	Knocks off the low-hanging instruction fruit.	2021-01-20 20:41:35 -05:00
Thomas Harte	6e618a6bb7	Adds a list of missing instructions. ... Not looking too bad; subject to not yet having a strategy for interrupts, timing, nothing yet implemented for timers, IO ports...	2021-01-20 20:37:35 -05:00
Thomas Harte	df1bc18fb3	Pushes ahead to what will be my first interaction with the T flag.	2021-01-20 20:27:09 -05:00
Thomas Harte	9f12ce2fb8	Corrects RTS, adds the remainder of the direct flag manipulations.	2021-01-20 20:16:55 -05:00
Thomas Harte	b9672c0669	Gets beyond a prima facie convincing JSR/RET.	2021-01-20 18:21:44 -05:00
Thomas Harte	e58608b25a	Gets as far as executing a first loop.	2021-01-20 18:15:24 -05:00
Thomas Harte	e502d76371	Corrects immediate instruction length, muddles through to having to parse a second program segment. ... Albeit with JSR not yet properly implemented.	2021-01-19 22:12:18 -05:00
Thomas Harte	b0c790f3c6	Adds enough flags seemingly to reach an ASL.	2021-01-19 21:54:15 -05:00
Thomas Harte	aa478cd222	Stops trying to force bit ID into the addressing mode.	2021-01-19 21:51:01 -05:00
Thomas Harte	c78c121159	Succeeds at executing a single instruction.	2021-01-18 20:16:01 -05:00
Thomas Harte	e71e506883	This assert is redundant; not worth an extra #include.	2021-01-18 17:56:40 -05:00
Thomas Harte	a601ac0cab	Corrects performer population, lookup, calls.	2021-01-18 17:53:14 -05:00
Thomas Harte	9b92753e0a	In theory this should 'execute' up to the first unconditional branch. ... Where execution means: do very little.	2021-01-18 17:11:11 -05:00
Thomas Harte	ec0018df79	Routes in the ADB keyboard ROM. This should get as far as parsing.	2021-01-18 16:59:49 -05:00
Thomas Harte	8b19c523cf	Starts to bend towards getting some performers in motion.	2021-01-18 16:45:52 -05:00
Thomas Harte	5ace61f9b9	Continues walking very slowly towards cached execution.	2021-01-18 11:20:45 -05:00
Thomas Harte	8a74f5911c	Minor reorganisation to finish the day.	2021-01-17 21:56:15 -05:00
Thomas Harte	4982430a29	Takes a run at most of the remaining addressing modes.	2021-01-17 21:52:16 -05:00
Thomas Harte	dea79c6dea	Adds missing #include.	2021-01-17 20:56:22 -05:00
Thomas Harte	ad03858c6e	Switches performers to member functions. Very slightly starts work on M50740 performers.	2021-01-17 20:53:11 -05:00
Thomas Harte	54b26c7991	Bends to using 8-bit lookups for M50740 instructions.	2021-01-17 20:03:36 -05:00
Thomas Harte	17c3a3eb4b	Seeks to switch to maintaining a bank of performers. ... My thinking here is that for really simple processors there'll be 256 or less, meaning that they can be stored by simple uint8_t; for every other processor I can currently think of it'll likely be uint16_t. Either way, that's a much better outcome than using plain pointers, which on architectures I currently build for will always be 8 bytes. For the simple processors I can get eight times as much into the cache; for the others four times.	2021-01-17 19:38:23 -05:00
Thomas Harte	5f413a38df	Switches all American-style dates. ... I'd failed to configure my new computer appropriately, it seems.	2021-01-16 22:09:19 -05:00
Thomas Harte	8860d0ff51	Starts to establish the CachingExecutor.	2021-01-16 22:06:16 -05:00
Thomas Harte	8bd471fa3c	Corrects recursive call.	2021-01-16 21:50:48 -05:00
Thomas Harte	cd6ac51aa6	Muddles along to generating functions. ... Albeit right now without a body.	2021-01-16 21:45:44 -05:00
Thomas Harte	10caa1a1fb	Steps gingerly towards execution.	2021-01-16 20:51:02 -05:00
Thomas Harte	722e0068ca	Adds additional exposition.	2021-01-16 20:10:20 -05:00
Thomas Harte	8f2eea8819	Corrects AccessType::Read.	2021-01-16 20:04:48 -05:00
Thomas Harte	3b2d65fa16	Adds access type declaration.	2021-01-16 20:04:01 -05:00
Thomas Harte	3dc36b704a	Starts on the next piece: parsers.	2021-01-16 19:54:40 -05:00
Thomas Harte	37a20e125c	Completes the M50740 decoder. ... Completely untested.	2021-01-15 22:47:52 -05:00
Thomas Harte	2910faf963	Adds missing #include.	2021-01-15 22:33:14 -05:00
Thomas Harte	1acb8c3c42	Completes the opcode map.	2021-01-15 22:24:37 -05:00
Thomas Harte	f667dd223f	Advances to 50% of the opcode map.	2021-01-15 22:05:34 -05:00
Thomas Harte	e0d90f69ec	Fills in the first quarter of the opcode map.	2021-01-15 21:58:46 -05:00
Thomas Harte	d82187bee2	Decides to shove bit number into AddressingMode.	2021-01-15 21:50:05 -05:00
Thomas Harte	3c20e1f037	Adds files for the M50740 and corrects namespace errors elsewhere.	2021-01-15 21:30:30 -05:00
Thomas Harte	9c2c918760	Better sorts by function, corrects TEST description.	2021-01-15 21:07:02 -05:00
Thomas Harte	47d20699d8	Completes list, ensures POP acts as documented.	2021-01-15 20:48:31 -05:00
Thomas Harte	e8ce70dccb	Chips further away at documentation.	2021-01-15 18:52:59 -05:00
Thomas Harte	fa4938f29c	Establishes the reason I'm sort-of documenting these.	2021-01-15 18:27:55 -05:00
Thomas Harte	ddb4bb1421	Better plans project layout.	2021-01-15 18:16:01 -05:00