Thomas Harte
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2a7fc86b15
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Enabled stricter warnings.
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2017-07-21 20:44:35 -04:00 |
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Thomas Harte
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8f72fc4a44
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Factored out from the UEF implementation the concept of being a tape that has a queue of pending pulses and manages that queue.
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2017-07-16 22:04:40 -04:00 |
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Thomas Harte
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238348c885
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Performed the initial wiring to announce that this application supports TZX files and to route them to the ZX80/81 static analyser. The TZX class itself does not yet do much beyond basic validation. I think it'll be easiest if it follows in UEF's footsteps in queuing up pulses ahead of time, so some factoring out is now required.
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2017-07-16 21:33:11 -04:00 |
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Thomas Harte
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7b5f93510b
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Fixed the DigitalPhaseLockedLoopBridge bridge, once again fixing tests.
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2017-07-16 20:55:57 -04:00 |
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Thomas Harte
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8ddd686049
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Removed redundant variable.
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2017-07-16 19:04:03 -04:00 |
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Thomas Harte
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2fb0aea990
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Updated the C1540 test vessel to the new world.
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2017-07-16 17:00:39 -04:00 |
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Thomas Harte
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279f4760d7
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Eliminated buffer_size_ as something explicitly stored, and reduced size of delegate call out.
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2017-07-16 15:01:39 -04:00 |
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Thomas Harte
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368bff1a82
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Added a shell class that will one day be able to parse CSW files, plus the logic and metadata to instantiate it when a CSW presents itself.
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2017-07-10 21:43:58 -04:00 |
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Thomas Harte
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3e5c209039
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Added basic Typer support for the ZX80 and '81.
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2017-07-09 22:00:34 -04:00 |
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Thomas Harte
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54efcb7e2f
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Made a game attempt at automatic motor control and ensured setting is initialised correctly from the user defaults.
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2017-07-08 19:31:20 -04:00 |
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Thomas Harte
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e2575d6de4
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Routed tape motor selections through to the C++ side of the world, and ensured that manual tape playback works properly.
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2017-07-08 19:21:12 -04:00 |
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Thomas Harte
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23e989e170
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This will likely do for the Swift/XIB side of things: the play/pause button is enabled or disabled as per the user's choice of automatic tape control, and toggles function when pressed. It communicates activity down to the Objective-C[++] layer, giving it a route through to the actual machine.
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2017-07-08 19:12:06 -04:00 |
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Thomas Harte
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28412150e6
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Added controls for controlling the tape motor of the ZX80/81, assuming I can find an automatic option.
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2017-07-08 17:59:33 -04:00 |
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Thomas Harte
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cb105fdeb4
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Took a first stab at high-res support.
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2017-06-22 22:48:17 -04:00 |
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Thomas Harte
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aec4fd066b
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I think I've definitively decided against this model of timing.
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2017-06-22 21:32:14 -04:00 |
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Thomas Harte
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95a6b0f85c
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Introduced an NMI/wait interrupt timing test, and adjusted the Z80 to conform to information posted by Wilf Rigter.
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2017-06-22 21:09:26 -04:00 |
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Thomas Harte
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644ef13acd
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Connected up the fast-tape GUI option for the ZX80 and '81.
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2017-06-22 20:20:31 -04:00 |
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Thomas Harte
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0e0ce379b4
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Renamed MachineCycle to PartialMachineCycle given that it mostly no longer intends to describe an entire machine cycle.
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2017-06-21 20:38:08 -04:00 |
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Thomas Harte
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36e8a11505
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Sought to simplify the way partial machine cycles are communicated, for ease of machine implementation. Also implemented the wait line.
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2017-06-21 20:32:08 -04:00 |
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Thomas Harte
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108da64562
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Fixed LD H, (HL) and LD L, (HL) by ensuring that whatever the subclass does goes to a temporary place before updating the address. Corrected the LD (IX+d), n machine cycle test for my new best-guess timing. This should leave only interrupt timing as currently amiss.
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2017-06-20 22:25:00 -04:00 |
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Thomas Harte
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184b371649
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Attempted to get to 'proper' timing for LD (IX+d),n, albeit that proper is a guess.
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2017-06-20 21:48:50 -04:00 |
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Thomas Harte
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27ac342928
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Corrected conditional call timing, and its test.
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2017-06-20 20:57:23 -04:00 |
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Thomas Harte
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6752f165db
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Added failing tests for both kinds of CALL.
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2017-06-19 22:03:29 -04:00 |
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Thomas Harte
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e05076b258
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Added tests for everything except CALL. All passing.
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2017-06-19 22:00:04 -04:00 |
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Thomas Harte
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fadbfdf801
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Added DJNZ test.
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2017-06-19 21:31:56 -04:00 |
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Thomas Harte
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cb277b8d1e
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Added JP and JR tests.
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2017-06-19 21:27:23 -04:00 |
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Thomas Harte
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234f14dbbe
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Tests were at fault; all passing now.
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2017-06-19 21:14:40 -04:00 |
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Thomas Harte
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99ede3a9ef
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BIT/SET (IX+d) were incorrectly encoded. Hence fixed BIT (IX+d).
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2017-06-19 21:04:14 -04:00 |
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Thomas Harte
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378233f53d
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Extended to BITs and SETs, accruing three new failures.
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2017-06-19 21:01:30 -04:00 |
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Thomas Harte
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f903408980
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Caught up on comments.
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2017-06-19 20:53:22 -04:00 |
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Thomas Harte
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b684254908
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Introduced further tests down to a failing attempt at RLC (IX+d). Made an initial attempt to fix, failed.
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2017-06-19 20:33:34 -04:00 |
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Thomas Harte
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351d90ca55
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Added tests down to INC IX. No additional failures yet, though I've yet to reach conditional CALL.
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2017-06-19 20:04:55 -04:00 |
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Thomas Harte
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23177df26a
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Added various tests of the basic ALU ops.
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2017-06-19 19:53:26 -04:00 |
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Thomas Harte
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ba15371948
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Introduced timing tests for LDI[R] and CPI[R], fixing a latent issue in the rejig of LD BC, nn while I'm here.
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2017-06-19 19:47:00 -04:00 |
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Thomas Harte
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8d60734737
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Added tests for EXX, EX (SP), HL and EX (SP), IX. The latter two currently being incorrect.
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2017-06-19 19:17:54 -04:00 |
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Thomas Harte
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002098d496
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The final two tests were at fault — expecting POPs to write rather than read. Fixed, so the subset of timing tests as-yet implemented now passes. Which means it's time to slog through further tests.
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2017-06-19 07:45:41 -04:00 |
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Thomas Harte
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85c5c4405a
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Ensured that wait states don't appear unless requested (TODO: requesting), and made the output of my timing tests a little easier to parse.
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2017-06-19 07:30:01 -04:00 |
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Thomas Harte
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d668879ba6
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Started trying to wade back to passing tests. Working on the new timing tests first, and focussing on getting the Objective-C test machine to compile bus operations into machine cycles, which means indicating phase to all-RAM delegates.
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2017-06-18 22:03:13 -04:00 |
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Thomas Harte
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e1a2580b2a
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Renamed BusOperation to MachineCycle::Operation.
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2017-06-17 21:53:45 -04:00 |
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Thomas Harte
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b6f51474ff
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Ensured that -description can handle the newly-captured bus actions.
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2017-06-17 18:20:30 -04:00 |
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Thomas Harte
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0f18768091
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Disabled attempts at bus activity matching within the FUSE tests, at least until I settle on exactly what I intend to do.
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2017-06-17 18:19:25 -04:00 |
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Thomas Harte
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50cd617bd9
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Ensured test raises only the intentional failure exceptions.
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2017-06-15 22:33:46 -04:00 |
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Thomas Harte
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838b818cd3
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Finished transcribing first page of machine cycle documentation; several failures contained.
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2017-06-15 22:19:49 -04:00 |
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Thomas Harte
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cf795562bf
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Continued filling in tests, fleshing out what the test machine captures as a result.
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2017-06-15 20:59:59 -04:00 |
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Thomas Harte
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ac37424878
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Set up a test class to allow me to discover which of the machine cycle sequences I'm in error on.
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2017-06-15 19:06:59 -04:00 |
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Thomas Harte
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aed2827e7b
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Implemented a rudimentary way to test that instructions take as long as the FUSE tests think they should. Hence discovered that the (HL)-accessing BIT, RES and SET weren't. Corrected.
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2017-06-12 22:22:00 -04:00 |
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Thomas Harte
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a48616a138
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Fixed reference to Swift-world MachineDocument for the ZX81 file type.
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2017-06-12 18:51:11 -04:00 |
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Thomas Harte
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8222aac9e3
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Added an official declaration of support for ZX81 files.
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2017-06-11 21:40:41 -04:00 |
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Thomas Harte
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77aa3c187e
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Rebranded ZX80O as ZX80O81P, with an eye to making it accept ZX81 .p files. Adjusted the initial selection part of the static analyser appropriately.
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2017-06-11 21:38:32 -04:00 |
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Thomas Harte
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8116f85479
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Allowed the static analyser to specify a ZX80 or 81, and a memory model. Neither is respected yet in the machine.
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2017-06-11 19:12:20 -04:00 |
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