Thomas Harte
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76f03900d2
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Implemented EX HL, (SP) so as, allowing for indexed pages, to bring issues below the psychological 100 barrier. To 99.
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2017-05-28 00:02:14 -04:00 |
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Thomas Harte
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9759a04c7d
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Timing fixes: the fetch-decode-execute pattern is now per-page, since that on [DD/FD]CB not only doesn't increment R but doesn't take four cycles, so is probably a normal read cycle. Adjusted timing all around.
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2017-05-27 23:54:06 -04:00 |
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Thomas Harte
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0d2d04e17b
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Seeking proper [F/D]DCB emulation: the offset comes before the final byte of opcode, and adding seems to overlap with the opcode fetch, which does not increment R. Also needs to duplicate the result to visible registers.
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2017-05-27 21:06:56 -04:00 |
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Thomas Harte
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98423c6e41
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Accepted FUSE's view of bits 3 & 5 from BIT and RES, reducing to 623 issues.
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2017-05-27 16:19:15 -04:00 |
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Thomas Harte
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33c3fa21e3
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Fixed (HL)/(In + d) CB page modify instructions. Reducing failures to 672.
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2017-05-27 15:54:24 -04:00 |
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Thomas Harte
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2141d52794
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Corrected typo. Now at 696 failures.
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2017-05-27 15:41:26 -04:00 |
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Thomas Harte
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16b8021401
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Made a stab at the CB pages.
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2017-05-27 15:39:22 -04:00 |
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Thomas Harte
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151b09b5ca
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Fixed various other obvious cases for indexing.
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2017-05-26 23:37:17 -04:00 |
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Thomas Harte
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9bc2b48d9b
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Found a form I like for indexed addressing, applying it only where obvious for now. Which eliminates more than a couple of hundred of remaining failures.
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2017-05-26 23:23:33 -04:00 |
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Thomas Harte
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ab8a98f1df
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Implemented RST.
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2017-05-26 07:29:19 -04:00 |
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Thomas Harte
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efe354a7b1
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Fixed half carry after logical operation.s
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2017-05-25 22:55:04 -04:00 |
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Thomas Harte
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d50d3fc837
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Implemented CPL, SCF and CCF.
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2017-05-25 22:51:08 -04:00 |
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Thomas Harte
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83ee92af1a
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Made DAA work sufficiently well for the FUSE test.
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2017-05-25 22:41:05 -04:00 |
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Thomas Harte
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ea0ad9fd87
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Took a shot at DAA, seemingly not to Fuse's liking though.
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2017-05-25 22:17:48 -04:00 |
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Thomas Harte
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ff3c60c0e1
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Implemented the conditional JRs.
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2017-05-25 21:51:30 -04:00 |
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Thomas Harte
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399703a471
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Implemented JR.
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2017-05-25 21:48:28 -04:00 |
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Thomas Harte
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82017c4aea
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Implemented DJNZ.
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2017-05-25 21:44:24 -04:00 |
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Thomas Harte
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bdf07c3dc9
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Implemented EX AF, AF'.
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2017-05-25 21:26:32 -04:00 |
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Thomas Harte
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598be24644
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Fixed overflow for 8-bit decrementing.
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2017-05-25 21:23:38 -04:00 |
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Thomas Harte
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c668ff9472
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Added incrementing of the refresh register.
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2017-05-25 21:01:52 -04:00 |
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Thomas Harte
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6575091a78
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Fixed Z80's ownership of its fetch-decode-execute program, its habit of scheduling invalidly when hitting an unrecognised operation and the test machine's habit of dereferencing invalidly.
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2017-05-22 21:50:34 -04:00 |
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Thomas Harte
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9e25d014d2
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Made an attempt to log bus activity for comparison with FUSE results.
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2017-05-22 19:49:38 -04:00 |
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Thomas Harte
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41d5dd8679
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Added a memory access delegate to the Z80 all-ram processor, to allow access patterns to be captured.
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2017-05-22 19:24:11 -04:00 |
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Thomas Harte
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c3ea6dc1f5
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Added respect for limiting to the requested number of cycles in the Z80.
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2017-05-22 19:15:55 -04:00 |
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Thomas Harte
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22afa509ca
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Got to a parsing and towards an attempt to run FUSE tests.
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2017-05-22 19:14:46 -04:00 |
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Thomas Harte
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f2aae72cc2
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Fixed the 16-bit ADCs and SBCs, added INC (HL) and DEC (HL). Zexall now enters a seemingly-infinite loop. Which is progress, at least.
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2017-05-21 20:43:36 -04:00 |
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Thomas Harte
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fe8db1873c
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Added 16-bit ADC and SBC table entries; once again extended logging.
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2017-05-21 20:32:06 -04:00 |
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Thomas Harte
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c66c715ac9
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Starts to try to figure out how to implemented the index register pages, but doesn't yet read offsets.
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2017-05-21 19:26:40 -04:00 |
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Thomas Harte
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5dcfd85642
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Added a compact and copy stage for instruction pages, both [mostly] eliminating the mistake of letting static data structures contain pointers to instance storage and opening the door for addition of the DD and FD pages.
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2017-05-21 19:15:52 -04:00 |
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Thomas Harte
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c70dfe1b09
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Implemented the two variations of loading between (nn) and SP.
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2017-05-21 13:20:28 -04:00 |
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Thomas Harte
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232c591655
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Threw in a little macro documentation and a missing macro.
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2017-05-21 13:13:21 -04:00 |
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Thomas Harte
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790614b544
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Added EI and DI.
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2017-05-21 12:53:17 -04:00 |
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Thomas Harte
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32c032cd97
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Implemented a couple of easy-to-add missing base page instructions.
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2017-05-21 10:18:43 -04:00 |
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Thomas Harte
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e48ee16366
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Continued cleaning efforts, added conditional RET.
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2017-05-21 10:13:59 -04:00 |
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Thomas Harte
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e92d936ce8
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Added conditional calls.
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2017-05-21 10:03:46 -04:00 |
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Thomas Harte
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4e210c5396
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Added LD A, (nn).
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2017-05-21 10:00:10 -04:00 |
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Thomas Harte
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3d3e60b1fc
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Implemented LD (HL), r.
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2017-05-21 09:56:41 -04:00 |
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Thomas Harte
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f3f0e2f1a9
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Implemented RRA and RRCA.
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2017-05-21 09:52:19 -04:00 |
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Thomas Harte
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08206eea56
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This logging has outlived its usefulness for now.
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2017-05-21 09:47:53 -04:00 |
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Thomas Harte
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78296246e8
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Added ALU n.
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2017-05-21 09:46:18 -04:00 |
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Thomas Harte
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85b5dd35b1
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Took a shot at 8-bit arithmetic.
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2017-05-21 09:43:17 -04:00 |
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Thomas Harte
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11cfaa3e3d
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Performed light syntactic cleaning on the first part of the base page table, eliminated redundant temporary variables, implemented 8-bit increment and decrement.
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2017-05-21 09:17:30 -04:00 |
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Thomas Harte
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103c863534
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Through temporarily dramatically increased logging, fixed conditional JP.
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2017-05-20 23:03:52 -04:00 |
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Thomas Harte
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6688f83226
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Took a shot at LDIR.
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2017-05-20 21:58:24 -04:00 |
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Thomas Harte
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01a064dd63
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Added an empty ED page.
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2017-05-20 17:29:30 -04:00 |
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Thomas Harte
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7b234078ae
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Implemented EX DE, HL and shuffled to allow instruction pages.
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2017-05-20 17:04:25 -04:00 |
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Thomas Harte
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add02a7897
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Added LD (nn), A, and reduced double logging to single for now.
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2017-05-19 23:13:28 -04:00 |
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Thomas Harte
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19167df692
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Consolidated and filled in AND and XOR.
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2017-05-19 23:03:34 -04:00 |
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Thomas Harte
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6766845e21
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Filled in most of the loads.
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2017-05-19 22:57:43 -04:00 |
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Thomas Harte
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bc3b5f3e35
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Added 16-bit INCs and DECs. Which don't set flags, so are easy.
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2017-05-19 22:13:36 -04:00 |
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Thomas Harte
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5fe23113ec
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Moved RET to the correct place, implemented POP AF.
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2017-05-19 22:03:12 -04:00 |
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Thomas Harte
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c55e1c1d17
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Implemented POP and therefore RET; corrected timing of PUSH.
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2017-05-19 21:59:45 -04:00 |
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Thomas Harte
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62b432c046
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Added the concept of a trap handler to the all-RAM processor and exposed it via the test Z80 classes.
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2017-05-19 21:20:28 -04:00 |
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Thomas Harte
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eae1f78221
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Implemented the main page pushes.
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2017-05-19 19:28:38 -04:00 |
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Thomas Harte
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11d05fb3b8
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Expanded a little on operations, added an implementation or two.
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2017-05-19 19:18:35 -04:00 |
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Thomas Harte
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58efca835f
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Sought to add a further opcode.
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2017-05-18 22:53:43 -04:00 |
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Thomas Harte
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99f2060fc1
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Further improved macros.
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2017-05-18 22:11:54 -04:00 |
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Thomas Harte
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5d3ebcb35a
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Made a first attempt at LD HL, (nn).
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2017-05-17 22:42:30 -04:00 |
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Thomas Harte
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509d011fbe
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Implemented JP, my first Z80 operation.
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2017-05-17 22:31:41 -04:00 |
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Thomas Harte
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17ffd604bf
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Made an attempt to get the Z80 at least as far as rejecting an opcode.
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2017-05-17 21:45:23 -04:00 |
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Thomas Harte
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1378ab7278
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Ensured initial program counter and stack pointer are correct for Zexall, fixed the Z80 to use a compile-time polymorphic call for bus access.
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2017-05-17 07:36:06 -04:00 |
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Thomas Harte
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87a021ec2d
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Made further attempt to get as fas as having the Z80 attempt to do something.
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2017-05-16 22:19:40 -04:00 |
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Thomas Harte
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7190f927b7
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Factored out the stuff that both all-RAM processors would share, rather than duplicating it.
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2017-05-16 21:28:17 -04:00 |
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Thomas Harte
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d559d8b901
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Continued edging towards getting the absolute basics of a testable Z80, for test-driven development. Corrected old-fashioned instance naming issues with the corresponding 6502 class and removed an unnecessary source file while at it.
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2017-05-16 21:19:17 -04:00 |
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Thomas Harte
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50bb4f0142
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There's finally a loop in here, at least.
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2017-05-15 22:25:52 -04:00 |
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Thomas Harte
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7da51602d5
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Moved flush, added run_for_cycles, which does nothing right now.
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2017-05-15 07:59:21 -04:00 |
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Thomas Harte
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5152517887
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Added the boilerplate stuff necessary to query registers.
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2017-05-15 07:55:53 -04:00 |
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Thomas Harte
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eb8a2de5d6
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Settled definitively on flush as more communicative than synchronise (and slightly more locale neutral); culled some more duplication from the Z80.
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2017-05-15 07:38:59 -04:00 |
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Thomas Harte
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f2a1a906ff
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Adapted what negligible amount there is of the z80 as per the new CPU namespace.
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2017-05-14 22:15:16 -04:00 |
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Thomas Harte
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0808e9b6fb
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Pulled the 6502 into a CPU namespace, making it an instance of something that has micro-opcodes and schedules them, and factoring out the formulation of a register pair.
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2017-05-14 22:08:15 -04:00 |
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Thomas Harte
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b81a2cc273
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First tentative steps towards adding a Z80 implementation.
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2017-05-14 17:46:41 -04:00 |
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