Thomas Harte
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327ab81436
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Fills in direct, x and (direct) tests, fixing implementation of the latter.
10 to go.
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2020-10-14 21:17:28 -04:00 |
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Thomas Harte
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b22aa5d699
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Starts transcribing the addressing examples I have into tests.
Correspondingly extends the exposed register set and test-machine addressing range.
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2020-10-13 21:38:30 -04:00 |
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Thomas Harte
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3e6a2adaaf
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Corrects absolute, x and absolute, y addressing modes.
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2020-10-13 20:30:39 -04:00 |
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Thomas Harte
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8f5537aaaa
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Attempts to resolve my direct-indirect addressing stumble.
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2020-10-13 20:21:53 -04:00 |
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Thomas Harte
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a15d4a156b
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Starts trying to ensure appropriate address wrapping.
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2020-10-12 22:33:43 -04:00 |
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Thomas Harte
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f529eadbec
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Corrects 16-bit read-modify-write.
Subject to the TODO proviso on 'correct'; has my 6502 prejudice pushed me into unrealistic bus signalling?
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2020-10-12 18:36:09 -04:00 |
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Thomas Harte
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5dc3cd3a2f
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Starts using Jeek816 for a basic native-mode audit. Fixes absolute long addressing.
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2020-10-11 22:02:46 -04:00 |
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Thomas Harte
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82797fd395
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Attempts to do the proper thing for interrupts.
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2020-10-11 21:10:44 -04:00 |
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Thomas Harte
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a0885ab7d0
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Implements STP and WAI.
Albeit still without fully-implemented reactions to exceptions in general.
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2020-10-11 17:56:55 -04:00 |
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Thomas Harte
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8eaf1303a3
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Attempts proactively to ensure proper RTI behaviour on the 65816.
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2020-10-11 15:25:13 -04:00 |
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Thomas Harte
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071ad6b767
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I don't think RTL is needed; JML looks like it covers it.
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2020-10-10 22:16:35 -04:00 |
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Thomas Harte
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0619e49eac
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Takes a short at TSB and TRB.
Three to go.
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2020-10-10 22:00:17 -04:00 |
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Thomas Harte
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b8848d8580
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Implements TCD, TDC, TCS, TSC.
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2020-10-10 21:43:05 -04:00 |
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Thomas Harte
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aface1f8be
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Implements XBA and XCE.
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2020-10-10 21:34:22 -04:00 |
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Thomas Harte
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28c8ba70c1
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Implements REP and SEP and exposes the MX flags generally.
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2020-10-10 21:23:59 -04:00 |
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Thomas Harte
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6892ac13e8
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Corrects BIT. All 65816-applicable Wolfgang Lorenz tests now pass.
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2020-10-10 17:47:33 -04:00 |
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Thomas Harte
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0fe09cd1e4
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Knocks SBC into producing likely results; disables Lorenz testing.
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2020-10-10 17:13:16 -04:00 |
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Thomas Harte
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da4702851f
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Fixes ADC.
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2020-10-10 16:29:48 -04:00 |
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Thomas Harte
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6efe4e1753
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Fixes AND, EOR, ORA. Takes an unsuccessful shot at ROL.
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2020-10-10 10:53:17 -04:00 |
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Thomas Harte
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536c4d45c1
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Adds additional 65816 tests, some failing; seeks to improve carry behaviour in ASL and ROL.
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2020-10-10 10:11:57 -04:00 |
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Thomas Harte
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290598429a
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Applies indirect page zero emulation mode addressing constraint to ix addressing.
Lorenz's LDA tests now pass in emulation mode.
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2020-10-09 23:22:48 -04:00 |
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Thomas Harte
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92e72959c3
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Makes corrections to ix addressing mode and shift/roll flags.
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2020-10-09 23:12:20 -04:00 |
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Thomas Harte
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c01bc784b9
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Slightly reduces branching.
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2020-10-09 22:21:55 -04:00 |
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Thomas Harte
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abcd86a294
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Fixes accumulator instructions.
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2020-10-09 22:18:22 -04:00 |
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Thomas Harte
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451f83ba51
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Corrects emulation-mode read-modify-writes not to empty the data buffer.
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2020-10-09 22:14:42 -04:00 |
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Thomas Harte
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b439f40fe2
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Corrects INC and DEC.
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2020-10-09 22:04:25 -04:00 |
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Thomas Harte
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968166b06d
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Resolves incorrectly flow after setting up an absolute address.
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2020-10-09 21:48:35 -04:00 |
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Thomas Harte
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0ed98cbfac
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Attempts to fix direct indirect indexed; not yet successful I think.
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2020-10-08 22:15:19 -04:00 |
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Thomas Harte
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7dde7cc743
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Implements altered direct indexed addressing in emulation mode.
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2020-10-08 22:02:14 -04:00 |
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Thomas Harte
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755627f12d
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Corrects direct addressing.
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2020-10-08 20:00:01 -04:00 |
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Thomas Harte
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f8004d7096
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Implements RTI, corrects TAY.
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2020-10-08 18:06:11 -04:00 |
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Thomas Harte
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0418f51ef2
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Takes a shot at emulation-mode 'exceptions'.
It's just RTI and correct decimal SBC left of the official 6502s now, I think.
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2020-10-08 17:52:13 -04:00 |
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Thomas Harte
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054e0af071
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Corrects RTS behaviour: the return address on the stack is off by one.
Dormann's tests now proceed to a BRK.
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2020-10-08 16:55:45 -04:00 |
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Thomas Harte
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907c3374c3
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Attempts to clean up my JMP/JSR mess.
Also takes a step forwards in decimal SBC, but it's not right yet.
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2020-10-08 16:48:46 -04:00 |
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Thomas Harte
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f83ee97439
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PHP pushes with the BRK flag set in emulation mode.
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2020-10-07 21:37:50 -04:00 |
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Thomas Harte
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19aea85184
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Corrects CMP, CPX, CPY carry flags.
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2020-10-07 21:23:29 -04:00 |
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Thomas Harte
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1ba0a117e7
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Corrects PLB, PLD, PLP.
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2020-10-07 20:23:53 -04:00 |
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Thomas Harte
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b510b9d337
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Adds PHD, PHK and 8-bit PHP and PLP.
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2020-10-07 20:13:12 -04:00 |
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Thomas Harte
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b608e11965
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Realises that not all non-incrementing PC fetches should be thrown away.
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2020-10-07 20:06:27 -04:00 |
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Thomas Harte
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f7b119ffe1
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Moves temporary logging, fixes branch instructions.
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2020-10-07 19:57:58 -04:00 |
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Thomas Harte
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a4cec95db1
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Corrects load and transfer flag oversights.
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2020-10-07 19:36:23 -04:00 |
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Thomas Harte
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84c4fa197b
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Corrects DEX mapping, notes new Dormann failure case.
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2020-10-07 18:48:03 -04:00 |
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Thomas Harte
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eac722cf59
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Implements enough of ADC and SBC for the Dormann test definitively to fail.
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2020-10-07 18:36:17 -04:00 |
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Thomas Harte
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7439a326a6
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Implements BIT (in regular and immediate forms).
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2020-10-07 18:15:18 -04:00 |
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Thomas Harte
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5ca1c0747f
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Generalises CMP to implement CPX and CPY.
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2020-10-07 18:09:56 -04:00 |
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Thomas Harte
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466ca38dfa
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Corrects TXY and TYX; kudos to PatrickvL for the spot!
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2020-10-07 18:05:42 -04:00 |
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Thomas Harte
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93b0839036
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Knocks out some transfer operations.
I'm possibly only seven or eight away from being able to test with complete official-opcode-only 6502 code?
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2020-10-06 22:29:34 -04:00 |
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Thomas Harte
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e068cbc103
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Implements CMP and fixes a zero-flag error on 16-bit operations.
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2020-10-06 21:47:26 -04:00 |
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Thomas Harte
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5c809e5fbf
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Implements rolls and shifts.
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2020-10-06 21:34:39 -04:00 |
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Thomas Harte
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3933bf49cf
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Implements BRL.
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2020-10-06 21:28:54 -04:00 |
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Thomas Harte
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7065ba4857
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Implements the single-byte branches.
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2020-10-06 21:24:43 -04:00 |
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Thomas Harte
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ebff83018e
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Implements the bitwise operators.
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2020-10-06 20:17:03 -04:00 |
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Thomas Harte
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9ce9167e3c
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Formalises work left to do.
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2020-10-06 19:12:19 -04:00 |
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Thomas Harte
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993eff1d3d
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Starts slowly, with flag manipulation.
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2020-10-06 16:25:30 -04:00 |
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Thomas Harte
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18e8d6ce06
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Makes an effort to factor out the 6502's [lazy] flags.
This is preparatory to deciding which instructions, if any, are worth factoring out.
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2020-10-05 22:23:33 -04:00 |
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Thomas Harte
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b7ba0d4327
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Attempts to complete all addressing modes.
So, if bugs didn't exist, it'd just be members of the Operation enum to go.
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2020-10-05 17:04:57 -04:00 |
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Thomas Harte
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825201f4f2
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Adds direct indirect.
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2020-10-04 22:11:41 -04:00 |
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Thomas Harte
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9a05c68ce7
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Attempts direct and direct indexed indirect.
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2020-10-04 22:06:25 -04:00 |
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Thomas Harte
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d8dccf2500
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Attempts a full implementation of MVN and MVP.
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2020-10-04 19:21:04 -04:00 |
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Thomas Harte
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b416aa640f
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Slightly tidies up, eliminating some store bugs.
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2020-10-04 19:12:04 -04:00 |
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Thomas Harte
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4ebf594b3b
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This should bring me up to absolute, y.
i.e. next is datasheet program 7.
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2020-10-04 19:02:47 -04:00 |
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Thomas Harte
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8a83024962
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Starts a dash towards just completing the addressing modes for now.
This brings me up to the end of absolute long (i.e. 4a on the datasheet).
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2020-10-04 18:52:46 -04:00 |
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Thomas Harte
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bdc1136b96
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Edges towards working short absolute addressing mode.
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2020-10-03 21:30:24 -04:00 |
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Thomas Harte
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b83d93abc2
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Accepts that whether instructions do 8- or 16-bit bus accesses depends on either M or X depending on the operation.
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2020-10-02 17:08:30 -04:00 |
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Thomas Harte
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78b3ec4b10
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The actual work begins: starts implementing 65816 micro-ops.
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2020-09-29 18:42:07 -04:00 |
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Thomas Harte
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ef1a514785
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Introduces 6502Selector, for picking either a 6502 or a 65816 based on a single template parameter.
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2020-09-28 21:35:46 -04:00 |
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Thomas Harte
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6635876e7e
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Performs a bare factoring out of the 6502 bus handler.
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2020-09-28 18:43:53 -04:00 |
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Thomas Harte
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5645f90abe
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Takes a minor first step towards actually performing 65816 instructions.
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2020-09-27 22:20:58 -04:00 |
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