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https://github.com/TomHarte/CLK.git
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Thomas Harte
82 lines
2.2 KiB
C++
82 lines
2.2 KiB
C++
//
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// Tube6502.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 03/11/2025.
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// Copyright © 2025 Thomas Harte. All rights reserved.
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//
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#pragma once
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#include "TubeProcessor.hpp"
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#include "Processors/6502Mk2/6502Mk2.hpp"
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#include "Machines/Utility/ROMCatalogue.hpp"
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#include <algorithm>
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namespace Acorn::Tube {
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template <typename ULAT>
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class Processor<ULAT, TubeProcessor::WDC65C02> {
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public:
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static constexpr auto ROM = ROM::Name::BBCMicro6502Tube110;
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void set_rom(std::vector<uint8_t> source) {
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source.resize(sizeof(rom_));
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std::copy(source.begin(), source.end(), rom_);
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}
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Processor(ULAT &ula) : m6502_(*this), ula_(ula) {}
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// By convention, these are cycles relative to the host's 2Mhz bus.
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// Multiply by 3/2 to turn that into the tube 6502's usual 3Mhz bus.
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void run_for(const Cycles cycles) {
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cycles_modulo_ += cycles * 3;
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m6502_.run_for(cycles_modulo_.divide(2));
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}
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template <CPU::MOS6502Mk2::BusOperation operation, typename AddressT>
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Cycles perform(const AddressT address, CPU::MOS6502Mk2::data_t<operation> value) {
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if(address >= 0xfef8 && address < 0xff00) {
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rom_visible_ = false;
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if constexpr (is_read(operation)) {
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value = ula_.parasite_read(address);
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} else {
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ula_.parasite_write(address, value);
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}
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} else {
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if constexpr (is_read(operation)) {
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constexpr uint16_t RomStart = sizeof(ram_) - sizeof(rom_);
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value = rom_visible_ && address >= RomStart ? rom_[address - RomStart] : ram_[address];
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} else {
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ram_[address] = value;
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}
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}
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return Cycles(1);
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}
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void set_irq(const bool active) { m6502_.template set<CPU::MOS6502Mk2::Line::IRQ>(active); }
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void set_nmi(const bool active) { m6502_.template set<CPU::MOS6502Mk2::Line::NMI>(active); }
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void set_reset(const bool reset) {
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m6502_.template set<CPU::MOS6502Mk2::Line::Reset>(reset);
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rom_visible_ |= reset;
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}
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private:
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uint8_t rom_[2048];
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uint8_t ram_[65536];
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Cycles cycles_modulo_;
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struct M6502Traits {
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static constexpr auto uses_ready_line = false;
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static constexpr auto pause_precision = CPU::MOS6502Mk2::PausePrecision::AnyCycle;
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using BusHandlerT = Processor;
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};
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CPU::MOS6502Mk2::Processor<CPU::MOS6502Mk2::Model::WDC65C02, M6502Traits> m6502_;
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bool rom_visible_ = true;
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ULAT &ula_;
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};
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};
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