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241 lines
7.1 KiB
C++
241 lines
7.1 KiB
C++
//
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// OperationMapper.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 17/03/2023.
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// Copyright © 2023 Thomas Harte. All rights reserved.
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//
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#pragma once
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// Cf. https://techheap.packetizer.com/processors/6809/6809Instructions.html
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//
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// Subject to corrections:
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//
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// * CWAI and the pushes and pulls at 0x3x are immediate, not inherent.
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namespace InstructionSet::M6809 {
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enum class AddressingMode {
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Illegal,
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Inherent,
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Immediate,
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Direct,
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Relative, // TODO: is it worth breaking this into 8- and 16-bit versions?
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Variant,
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Indexed,
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Extended,
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};
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enum class Operation {
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None,
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SUBB, CMPB, SBCB, ADDD, ANDB, BITB, LDB, STB,
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EORB, ADCB, ORB, ADDB, LDD, STD, LDU, STU,
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SUBA, CMPA, SBCA, SUBD, ANDA, BITA, LDA, STA,
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EORA, ADCA, ORA, ADDA, CMPX, JSR, LDX, STX,
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BSR,
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NEG, COM, LSR, ROR, ASR,
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LSL, ROL, DEC, INC, TST, JMP, CLR,
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NEGA, COMA, LSRA, RORA, ASRA,
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LSLA, ROLA, DECA, INCA, TSTA, CLRA,
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NEGB, COMB, LSRB, RORB, ASRB,
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LSLB, ROLB, DECB, INCB, TSTB, CLRB,
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LEAX, LEAY, LEAS, LEAU,
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PSHS, PULS, PSHU, PULU,
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RTS, ABX, RTI,
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CWAI, MUL, RESET, SWI,
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BRA, BRN, BHI, BLS, BCC, BCS, BNE, BEQ,
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BVC, BVS, BPL, BMI, BGE, BLT, BGT, BLE,
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Page1, Page2, NOP, SYNC, LBRA, LBSR,
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DAA, ORCC, ANDCC, SEX, EXG, TFR,
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LBRN, LBHI, LBLS, LBCC, LBCS, LBNE, LBEQ,
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LBVC, LBVS, LBPL, LBMI, LBGE, LBLT, LBGT, LBLE,
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SWI2, CMPD, CMPY, LDY, STY, LDS, STS,
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SWI3, CMPU, CMPS,
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};
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enum class Page {
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Page0, Page1, Page2,
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};
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/*!
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Calls @c scheduler.schedule<Operation,AddressingMode> to describe the instruction
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defined by opcode @c i on page @c page.
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*/
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template <Page page> struct OperationMapper {
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template <int i, typename SchedulerT> void dispatch(SchedulerT &scheduler);
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};
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template <>
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template <int i, typename SchedulerT> void OperationMapper<Page::Page0>::dispatch(SchedulerT &s) {
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using AM = AddressingMode;
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using O = Operation;
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constexpr auto upper = (i >> 4) & 0xf;
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constexpr auto lower = (i >> 0) & 0xf;
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constexpr AddressingMode modes[] = {
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AM::Immediate, AM::Direct, AM::Indexed, AM::Extended
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};
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constexpr AddressingMode mode = modes[(i >> 4) & 3];
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switch(upper) {
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default: break;
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case 0x1: {
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constexpr Operation operations[] = {
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O::Page1, O::Page2, O::NOP, O::SYNC, O::None, O::None, O::LBRA, O::LBSR,
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O::None, O::DAA, O::ORCC, O::None, O::ANDCC, O::SEX, O::EXG, O::TFR,
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};
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constexpr AddressingMode modes[] = {
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AM::Variant, AM::Variant, AM::Inherent, AM::Inherent,
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AM::Illegal, AM::Illegal, AM::Relative, AM::Relative,
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AM::Illegal, AM::Inherent, AM::Immediate, AM::Illegal,
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AM::Immediate, AM::Inherent, AM::Inherent, AM::Inherent,
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};
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s.template schedule<operations[lower], modes[lower]>();
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} break;
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case 0x2: {
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constexpr Operation operations[] = {
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O::BRA, O::BRN, O::BHI, O::BLS, O::BCC, O::BCS, O::BNE, O::BEQ,
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O::BVC, O::BVS, O::BPL, O::BMI, O::BGE, O::BLT, O::BGT, O::BLE,
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};
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s.template schedule<operations[lower], AM::Relative>();
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} break;
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case 0x3: {
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constexpr Operation operations[] = {
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O::LEAX, O::LEAY, O::LEAS, O::LEAU, O::PSHS, O::PULS, O::PSHU, O::PULU,
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O::None, O::RTS, O::ABX, O::RTI, O::CWAI, O::MUL, O::RESET, O::SWI,
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};
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constexpr auto op = operations[lower];
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switch(lower) {
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case 0x0: case 0x1: case 0x2: case 0x3:
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s.template schedule<op, AM::Indexed>();
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break;
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case 0x4: case 0x5: case 0x6: case 0x7: case 0xc:
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s.template schedule<op, AM::Immediate>();
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break;
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case 0x8:
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s.template schedule<op, AM::Illegal>();
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break;
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default:
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s.template schedule<op, AM::Inherent>();
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break;
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}
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} break;
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case 0x4: {
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constexpr Operation operations[] = {
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O::NEGA, O::None, O::None, O::COMA, O::LSRA, O::None, O::RORA, O::ASRA,
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O::LSLA, O::ROLA, O::DECA, O::None, O::INCA, O::TSTA, O::None, O::CLRA,
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};
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constexpr auto op = operations[lower];
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s.template schedule<op, op == O::None ? AM::Illegal : AM::Inherent>();
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} break;
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case 0x5: {
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constexpr Operation operations[] = {
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O::NEGB, O::None, O::None, O::COMB, O::LSRB, O::None, O::RORB, O::ASRB,
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O::LSLB, O::ROLB, O::DECB, O::None, O::INCB, O::TSTB, O::None, O::CLRB,
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};
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constexpr auto op = operations[lower];
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s.template schedule<op, op == O::None ? AM::Illegal : AM::Inherent>();
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} break;
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case 0x0: case 0x6: case 0x7: {
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constexpr Operation operations[] = {
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O::NEG, O::None, O::None, O::COM, O::LSR, O::None, O::ROR, O::ASR,
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O::LSL, O::ROL, O::DEC, O::None, O::INC, O::TST, O::JMP, O::CLR,
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};
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constexpr auto op = operations[lower];
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s.template schedule<op, op == O::None ? AM::Illegal : upper == 0 ? AM::Direct : mode>();
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} break;
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case 0x8: case 0x9: case 0xa: case 0xb: {
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constexpr Operation operations[] = {
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O::SUBA, O::CMPA, O::SBCA, O::SUBD, O::ANDA, O::BITA, O::LDA, O::STA,
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O::EORA, O::ADCA, O::ORA, O::ADDA, O::CMPX, O::JSR, O::LDX, O::STX,
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};
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if(i == 0x8d) s.template schedule<O::BSR, AM::Relative>();
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else s.template schedule<operations[lower], mode>();
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} break;
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case 0xc: case 0xd: case 0xe: case 0xf: {
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constexpr Operation operations[] = {
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O::SUBB, O::CMPB, O::SBCB, O::ADDD, O::ANDB, O::BITB, O::LDB, O::STB,
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O::EORB, O::ADCB, O::ORB, O::ADDB, O::LDD, O::STD, O::LDU, O::STU,
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};
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s.template schedule<operations[lower], mode>();
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} break;
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}
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}
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template <>
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template <int i, typename SchedulerT> void OperationMapper<Page::Page1>::dispatch(SchedulerT &s) {
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using AM = AddressingMode;
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using O = Operation;
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constexpr AddressingMode modes[] = {
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AM::Immediate, AM::Direct, AM::Indexed, AM::Extended
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};
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constexpr auto mode = modes[(i >> 4) & 3];
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if constexpr (i >= 0x21 && i < 0x30) {
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constexpr Operation operations[] = {
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O::LBRN, O::LBHI, O::LBLS, O::LBCC, O::LBCS, O::LBNE, O::LBEQ,
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O::LBVC, O::LBVS, O::LBPL, O::LBMI, O::LBGE, O::LBLT, O::LBGT, O::LBLE,
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};
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s.template schedule<operations[i - 0x21], AM::Relative>();
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} else switch(i) {
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default: s.template schedule<O::None, AM::Illegal>(); break;
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case 0x3f: s.template schedule<O::SWI2, AM::Inherent>(); break;
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case 0x83: case 0x93: case 0xa3: case 0xb3:
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s.template schedule<O::CMPD, mode>();
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break;
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case 0x8c: case 0x9c: case 0xac: case 0xbc:
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s.template schedule<O::CMPY, mode>();
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break;
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case 0x8e: case 0x9e: case 0xae: case 0xbe:
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s.template schedule<O::LDY, mode>();
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break;
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case 0x9f: case 0xaf: case 0xbf:
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s.template schedule<O::STY, mode>();
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break;
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case 0xce: case 0xde: case 0xee: case 0xfe:
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s.template schedule<O::LDS, mode>();
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break;
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case 0xdf: case 0xef: case 0xff:
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s.template schedule<O::STS, mode>();
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break;
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}
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}
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template <>
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template <int i, typename SchedulerT> void OperationMapper<Page::Page2>::dispatch(SchedulerT &s) {
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using AM = AddressingMode;
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using O = Operation;
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constexpr AddressingMode modes[] = {
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AM::Immediate, AM::Direct, AM::Indexed, AM::Extended
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};
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constexpr auto mode = modes[(i >> 4) & 3];
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switch(i) {
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default: s.template schedule<O::None, AM::Illegal>(); break;
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case 0x3f: s.template schedule<O::SWI3, AM::Inherent>(); break;
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case 0x83: case 0x93: case 0xa3: case 0xb3:
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s.template schedule<O::CMPU, mode>();
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break;
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case 0x8c: case 0x9c: case 0xac: case 0xbc:
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s.template schedule<O::CMPS, mode>();
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break;
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}
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}
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}
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