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703065a0a5
Seemingly sufficiently to pass the VICE test (which I've transcribed), though with some guesswork.
365 lines
16 KiB
Swift
365 lines
16 KiB
Swift
//
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// 6522Tests.swift
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// Clock Signal
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//
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// Created by Thomas Harte on 18/06/2016.
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// Copyright 2016 Thomas Harte. All rights reserved.
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//
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import XCTest
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import Foundation
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class MOS6522Tests: XCTestCase {
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private var m6522: MOS6522Bridge!
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override func setUp() {
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m6522 = MOS6522Bridge()
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}
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// MARK: Timer tests
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func testTimerCount() {
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// set timer 1 to a value of m652200a
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m6522.setValue(10, forRegister: 4)
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m6522.setValue(0, forRegister: 5)
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// complete the setting cycle
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m6522.run(forHalfCycles: 2)
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// run for 5 cycles
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m6522.run(forHalfCycles: 10)
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// check that the timer has gone down by 5
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XCTAssert(m6522.value(forRegister: 4) == 5, "Low order byte should be 5; was \(m6522.value(forRegister: 4))")
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XCTAssert(m6522.value(forRegister: 5) == 0, "High order byte should be 0; was \(m6522.value(forRegister: 5))")
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}
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func testTimerLatches() {
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// set timer 2 to $1020
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m6522.setValue(0x10, forRegister: 8)
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m6522.setValue(0x20, forRegister: 9)
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// change the low-byte latch
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m6522.setValue(0x40, forRegister: 8)
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// complete the cycle
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m6522.run(forHalfCycles: 2)
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// chek that the new latched value hasn't been copied
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XCTAssert(m6522.value(forRegister: 8) == 0x10, "Low order byte should be 0x10; was \(m6522.value(forRegister: 8))")
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XCTAssert(m6522.value(forRegister: 9) == 0x20, "High order byte should be 0x20; was \(m6522.value(forRegister: 9))")
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// write the low-byte latch
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m6522.setValue(0x50, forRegister: 9)
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// complete the cycle
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m6522.run(forHalfCycles: 2)
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// chek that the latched value has been copied
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XCTAssert(m6522.value(forRegister: 8) == 0x40, "Low order byte should be 0x50; was \(m6522.value(forRegister: 8))")
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XCTAssert(m6522.value(forRegister: 9) == 0x50, "High order byte should be 0x40; was \(m6522.value(forRegister: 9))")
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}
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func testTimerReload() {
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// set timer 1 to a value of m6522010, enable repeating mode
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m6522.setValue(16, forRegister: 4)
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m6522.setValue(0, forRegister: 5)
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m6522.setValue(0x40, forRegister: 11)
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m6522.setValue(0x40 | 0x80, forRegister: 14)
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// complete the cycle to set initial values
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m6522.run(forHalfCycles: 2)
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// run for 16 cycles
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m6522.run(forHalfCycles: 32)
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// check that the timer has gone down to 0 but not yet triggered an interrupt
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XCTAssert(m6522.value(forRegister: 4) == 0, "Low order byte should be 0; was \(m6522.value(forRegister: 4))")
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XCTAssert(m6522.value(forRegister: 5) == 0, "High order byte should be 0; was \(m6522.value(forRegister: 5))")
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XCTAssert(!m6522.irqLine, "IRQ should not yet be active")
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// check that two half-cycles later the timer is $ffff but IRQ still hasn't triggered
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m6522.run(forHalfCycles: 2)
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XCTAssert(m6522.value(forRegister: 4) == 0xff, "Low order byte should be 0xff; was \(m6522.value(forRegister: 4))")
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XCTAssert(m6522.value(forRegister: 5) == 0xff, "High order byte should be 0xff; was \(m6522.value(forRegister: 5))")
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XCTAssert(!m6522.irqLine, "IRQ should not yet be active")
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// check that one half-cycle later the timer is still $ffff and IRQ has triggered...
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m6522.run(forHalfCycles: 1)
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XCTAssert(m6522.irqLine, "IRQ should be active")
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XCTAssert(m6522.value(forRegister: 4) == 0xff, "Low order byte should be 0xff; was \(m6522.value(forRegister: 4))")
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XCTAssert(m6522.value(forRegister: 5) == 0xff, "High order byte should be 0xff; was \(m6522.value(forRegister: 5))")
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// ... but that reading the timer cleared the interrupt
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XCTAssert(!m6522.irqLine, "IRQ should be active")
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// check that one half-cycles later the timer has reloaded
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m6522.run(forHalfCycles: 1)
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XCTAssert(m6522.value(forRegister: 4) == 0x10, "Low order byte should be 0x10; was \(m6522.value(forRegister: 4))")
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XCTAssert(m6522.value(forRegister: 5) == 0x00, "High order byte should be 0x00; was \(m6522.value(forRegister: 5))")
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}
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// MARK: PB7 timer 1 tests
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// These follow the same logic and check for the same results as the VICE VIC-20 via_pb7 tests.
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// Perfoms:
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//
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// (1) establish initial ACR and port B output value, and grab port B input value.
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// (2) start timer 1, grab port B input value.
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// (3) set final ACR, grab port B input value.
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// (4) allow timer 1 to expire, grab port B input value.
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private func runTest(startACR: UInt8, endACR: UInt8, portBOutput: UInt8) -> [UInt8] {
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var result: [UInt8] = []
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// Clear all register values.
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for n: UInt in 0...15 {
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m6522.setValue(0, forRegister: n)
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}
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m6522.run(forHalfCycles: 2)
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// Set data direction and current port B value.
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m6522.setValue(0xff, forRegister: 2)
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m6522.run(forHalfCycles: 2)
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m6522.setValue(portBOutput, forRegister: 0)
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m6522.run(forHalfCycles: 2)
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// Set initial ACR and grab the current port B value.
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m6522.setValue(startACR, forRegister: 0xb)
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m6522.run(forHalfCycles: 2)
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result.append(m6522.value(forRegister: 0))
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m6522.run(forHalfCycles: 2)
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// Start timer 1 and grab the value.
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m6522.setValue(1, forRegister: 0x5)
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m6522.run(forHalfCycles: 2)
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result.append(m6522.value(forRegister: 0))
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m6522.run(forHalfCycles: 2)
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// Set the final ACR value and grab value.
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m6522.setValue(endACR, forRegister: 0xb)
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m6522.run(forHalfCycles: 2)
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result.append(m6522.value(forRegister: 0))
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m6522.run(forHalfCycles: 2)
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// Make sure timer 1 has expired.
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m6522.run(forHalfCycles: 512)
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// Grab the final value.
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result.append(m6522.value(forRegister: 0))
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return result
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}
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func testTimer1PB7() {
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// Original top row. [original Vic-20 screen output in comments on the right]
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XCTAssertEqual(runTest(startACR: 0x00, endACR: 0x00, portBOutput: 0x00), [0x00, 0x00, 0x00, 0x00]) // @@@@ (i.e. 0, 0, 0, 0)
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XCTAssertEqual(runTest(startACR: 0x00, endACR: 0x40, portBOutput: 0x00), [0x00, 0x00, 0x00, 0x00]) // @@@@ (i.e. 0, 0, 0, 0)
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XCTAssertEqual(runTest(startACR: 0x00, endACR: 0x80, portBOutput: 0x00), [0x00, 0x00, 0x80, 0x00]) // @@b@ (i.e. 0, 0, 1, 0)
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XCTAssertEqual(runTest(startACR: 0x00, endACR: 0xc0, portBOutput: 0x00), [0x00, 0x00, 0x80, 0x00]) // @@b@ (i.e. 0, 0, 1, 0)
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XCTAssertEqual(runTest(startACR: 0x00, endACR: 0x00, portBOutput: 0xff), [0xff, 0xff, 0xff, 0xff]) // cccc (i.e. 1, 1, 1, 1)
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XCTAssertEqual(runTest(startACR: 0x00, endACR: 0x40, portBOutput: 0xff), [0xff, 0xff, 0xff, 0xff]) // cccc (i.e. 1, 1, 1, 1)
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XCTAssertEqual(runTest(startACR: 0x00, endACR: 0x80, portBOutput: 0xff), [0xff, 0xff, 0xff, 0x7f]) // ccca (i.e. 1, 1, 1, 0)
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XCTAssertEqual(runTest(startACR: 0x00, endACR: 0xc0, portBOutput: 0xff), [0xff, 0xff, 0xff, 0x7f]) // ccca (i.e. 1, 1, 1, 0)
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// Second row. [same output as first row]
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XCTAssertEqual(runTest(startACR: 0x40, endACR: 0x00, portBOutput: 0x00), [0x00, 0x00, 0x00, 0x00]) // @@@@
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XCTAssertEqual(runTest(startACR: 0x40, endACR: 0x40, portBOutput: 0x00), [0x00, 0x00, 0x00, 0x00]) // @@@@
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XCTAssertEqual(runTest(startACR: 0x40, endACR: 0x80, portBOutput: 0x00), [0x00, 0x00, 0x80, 0x00]) // @@b@
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XCTAssertEqual(runTest(startACR: 0x40, endACR: 0xc0, portBOutput: 0x00), [0x00, 0x00, 0x80, 0x00]) // @@b@
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XCTAssertEqual(runTest(startACR: 0x40, endACR: 0x00, portBOutput: 0xff), [0xff, 0xff, 0xff, 0xff]) // cccc
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XCTAssertEqual(runTest(startACR: 0x40, endACR: 0x40, portBOutput: 0xff), [0xff, 0xff, 0xff, 0xff]) // cccc
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XCTAssertEqual(runTest(startACR: 0x40, endACR: 0x80, portBOutput: 0xff), [0xff, 0xff, 0xff, 0x7f]) // ccca
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XCTAssertEqual(runTest(startACR: 0x40, endACR: 0xc0, portBOutput: 0xff), [0xff, 0xff, 0xff, 0x7f]) // ccca
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// Third row.
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XCTAssertEqual(runTest(startACR: 0x80, endACR: 0x00, portBOutput: 0x00), [0x80, 0x00, 0x00, 0x00]) // b@@@ (i.e. 1, 0, 0, 0)
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XCTAssertEqual(runTest(startACR: 0x80, endACR: 0x40, portBOutput: 0x00), [0x80, 0x00, 0x00, 0x00]) // b@@@ (i.e. 1, 0, 0, 0)
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XCTAssertEqual(runTest(startACR: 0x80, endACR: 0x80, portBOutput: 0x00), [0x80, 0x00, 0x00, 0x80]) // b@@b (i.e. 1, 0, 0, 1)
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XCTAssertEqual(runTest(startACR: 0x80, endACR: 0xc0, portBOutput: 0x00), [0x80, 0x00, 0x00, 0x80]) // b@@b (i.e. 1, 0, 0, 1)
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XCTAssertEqual(runTest(startACR: 0x80, endACR: 0x00, portBOutput: 0xff), [0xff, 0x7f, 0xff, 0xff]) // cacc (i.e. 1, 0, 1, 1)
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XCTAssertEqual(runTest(startACR: 0x80, endACR: 0x40, portBOutput: 0xff), [0xff, 0x7f, 0xff, 0xff]) // cacc (i.e. 1, 0, 1, 1)
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XCTAssertEqual(runTest(startACR: 0x80, endACR: 0x80, portBOutput: 0xff), [0xff, 0x7f, 0x7f, 0xff]) // caac (i.e. 1, 0, 0, 1)
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XCTAssertEqual(runTest(startACR: 0x80, endACR: 0xc0, portBOutput: 0xff), [0xff, 0x7f, 0x7f, 0xff]) // caac (i.e. 1, 0, 0, 1)
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// Final row. [same output as third row]
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XCTAssertEqual(runTest(startACR: 0xc0, endACR: 0x00, portBOutput: 0x00), [0x80, 0x00, 0x00, 0x00]) // b@@@
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XCTAssertEqual(runTest(startACR: 0xc0, endACR: 0x40, portBOutput: 0x00), [0x80, 0x00, 0x00, 0x00]) // b@@@
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XCTAssertEqual(runTest(startACR: 0xc0, endACR: 0x80, portBOutput: 0x00), [0x80, 0x00, 0x00, 0x80]) // b@@b
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XCTAssertEqual(runTest(startACR: 0xc0, endACR: 0xc0, portBOutput: 0x00), [0x80, 0x00, 0x00, 0x80]) // b@@b
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XCTAssertEqual(runTest(startACR: 0xc0, endACR: 0x00, portBOutput: 0xff), [0xff, 0x7f, 0xff, 0xff]) // cacc
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XCTAssertEqual(runTest(startACR: 0xc0, endACR: 0x40, portBOutput: 0xff), [0xff, 0x7f, 0xff, 0xff]) // cacc
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XCTAssertEqual(runTest(startACR: 0xc0, endACR: 0x80, portBOutput: 0xff), [0xff, 0x7f, 0x7f, 0xff]) // caac
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XCTAssertEqual(runTest(startACR: 0xc0, endACR: 0xc0, portBOutput: 0xff), [0xff, 0x7f, 0x7f, 0xff]) // caac
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// Conclusions:
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//
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// after inital ACR and port B value: [original data if not in PB7 output mode, otherwise 1]
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// after starting timer 1: [original data if not in PB7 output mode, otherwise 0]
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// after final ACR value: [original data if not in PB7 output mode, 1 if has transitioned to PB7 mode, 0 if was already in PB7 mode]
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// after timer 1 expiry: [original data if not in PB7 mode, 1 if timer has expired while in PB7 mode]
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//
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// i.e.
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// (1) there is separate storage for the programmer-set PB7 and the timer output;
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// (2) the timer output is reset upon a timer write only if PB7 output is enabled;
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// (3) expiry toggles the output.
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}
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// MARK: Data direction tests
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func testDataDirection() {
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// set low four bits of register B as output, the top four as input
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m6522.setValue(0xf0, forRegister: 2)
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// ask to output 0x8c
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m6522.setValue(0x8c, forRegister: 0)
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// complete the cycle
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m6522.run(forHalfCycles: 2)
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// set current input as 0xda
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m6522.portBInput = 0xda
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// test that the result of reading register B is therefore 0x8a
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XCTAssert(m6522.value(forRegister: 0) == 0x8a, "Data direction register should mix input and output; got \(m6522.value(forRegister: 0))")
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}
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func testShiftDisabled() {
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/*
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Mode 0 disables the Shift Register. In this mode the microprocessor can
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write or read the SR and the SR will shift on each CB1 positive edge
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shifting in the value on CB2. In this mode the SR Interrupt Flag is
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disabled (held to a logic 0).
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*/
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}
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func testShiftInUnderT2() {
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/*
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In mode 1, the shifting rate is controlled by the low order 8 bits of T2
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(Figure 22). Shift pulses are generated on the CB1 pin to control shifting
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in external devices. The time between transitions of this output clock is a
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function of the system clock period and the contents of the low order T2
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latch (N).
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The shifting operation is triggered by the read or write of the SR if the
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SR flag is set in the IFR. Otherwise the first shift will occur at the next
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time-out of T2 after a read or write of the SR. Data is shifted first into
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the low order bit of SR and is then shifted into the next higher order bit
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of the shift register on the negative-going edge of each clock pulse. The
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input data should change before the positive-going edge of the CB1 clock
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pulse. This data is shifted into shift register during the 02 clock cycle
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following the positive-going edge of the CB1 clock pulse. After 8 CB1 clock
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pulses, the shift register interrupt flag will set and IRQ will go low.
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*/
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}
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func testShiftInUnderPhase2() {
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/*
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In mode 2, the shift rate is a direct function of the system clock
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frequency (Figure 23). CB1 becomes an output which generates shift pulses
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for controlling external devices. Timer 2 operates as an independent
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interval timer and has no effect on SR. The shifting operation is triggered
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by reading or writing the Shift Register. Data is shifted, first into bit 0
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and is then shifted into the next higher order bit of the shift register on
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the trailing edge of each 02 clock pulse. After 8 clock pulses, the shift
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register interrupt flag will be set, and the output clock pulses on CB1
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will stop.
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*/
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}
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func testShiftInUnderCB1() {
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/*
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In mode 3, external pin CB1 becomes an input (Figure 24). This allows an
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external device to load the shift register at its own pace. The shift
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register counter will interrupt the processor each time 8 bits have been
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shifted in. However the shift register counter does not stop the shifting
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operation; it acts simply as a pulse counter. Reading or writing the Shift
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Register resets the Interrupt Flag and initializes the SR counter to count
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another 8 pulses.
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Note that the data is shifted during the first system clock cycle
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following the positive-going edge of the CB1 shift pulse. For this reason,
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data must be held stable during the first full cycle following CB1 going
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high.
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*/
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}
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func testShiftOutUnderT2FreeRunning() {
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/*
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Mode 4 is very similar to mode 5 in which the shifting rate is set by T2.
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However, in mode 4 the SR Counter does not stop the shifting operation
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(Figure 25). Since the Shift Register bit 7 (SR7) is recirculated back into
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bit 0, the 8 bits loaded into the Shift Register will be clocked onto CB2
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repetitively. In this mode the Shift Register Counter is disabled.
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*/
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}
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func testShiftOutUnderT2() {
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/*
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In mode 5, the shift rate is controlled by T2 (as in mode 4). The shifting
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operation is triggered by the read or write of the SR if the SR flag is set
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in the IFR (Figure 26). Otherwise the first shift will occur at the next
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time-out of T2 after a read or write of the SR. However, with each read or
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write of the shift register the SR Counter is reset and 8 bits are shifted
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onto CB2. At the same time, 8 shift pulses are generated on CB1 to control
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shifting in external devices. After the 8 shift pulses, the shifting is
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disabled, the SR Interrupt Flag is set and CB2 remains at the last data
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level.
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*/
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}
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func testShiftOutUnderPhase2() {
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/*
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In mode 6, the shift rate is controlled by the 02 system clock (Figure 27).
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(... and I'm assuming the same behaviour as shift out under control of T2
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otherwise, based on original context)
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*/
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// Set the shift register to a non-zero something.
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m6522.setValue(0xaa, forRegister: 10)
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// Set shift register mode 6.
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m6522.setValue(6 << 2, forRegister: 11)
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// Make sure the shift register's interrupt bit is set.
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m6522.run(forHalfCycles: 16)
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XCTAssertEqual(m6522.value(forRegister: 13) & 0x04, 0x04)
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// Test that output is now inhibited: CB2 should remain unchanged.
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let initialOutput = m6522.value(forControlLine: .two, port: .B)
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for _ in 1...8 {
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m6522.run(forHalfCycles: 2)
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XCTAssertEqual(m6522.value(forControlLine: .two, port: .B), initialOutput)
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}
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// Set a new value to the shift register.
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m6522.setValue(0x16, forRegister: 10)
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// Test that the new value is shifted out.
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var output = 0
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for _ in 1..<8 {
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m6522.run(forHalfCycles: 2)
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output = (output << 1) | (m6522.value(forControlLine: .two, port: .B) ? 1 : 0)
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}
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XCTAssertEqual(output, 0x16)
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}
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func testShiftOutUnderCB1() {
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/*
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In mode 7, shifting is controlled by pulses applied to the CB1 pin by an
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external device (Figure 28). The SR counter sets the SR Interrupt Flag each
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time it counts 8 pulses but it does not disable the shifting function. Each
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time the microprocessor, writes or reads the shift register, the SR
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Interrupt Flag is reset and the SR counter is initialized to begin counting
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the next 8 shift pulses on pin CB1. After 8 shift pulses, the Interrupt
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Flag is set. The microprocessor can then load the shift register with the
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next byte of data.
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*/
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}
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}
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