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mirror of https://github.com/TomHarte/CLK.git synced 2024-11-26 08:49:37 +00:00
CLK/Components
2021-11-24 16:15:27 -05:00
..
1770 WD1770: switch motor on even if spin-up is disabled. 2021-06-21 23:26:55 -04:00
5380 Adds further [[fallthrough]] attributes. 2020-06-19 23:36:51 -04:00
6522 Eliminate unused #includes. 2021-07-18 11:35:57 -04:00
6526 Adds basic shift input. 2021-11-07 05:18:54 -08:00
6532 Starts to add Qt target; resolves many build warnings. 2020-05-30 00:37:06 -04:00
6560 Splits the lowpass filter into push and pull variants. 2021-11-21 15:37:29 -05:00
6845 Further doubles down on construction syntax for type conversions. 2020-05-09 23:00:39 -04:00
6850 Introduce the principle that a Serial::Line can be two-wire — clock + data. 2021-11-06 16:54:20 -07:00
8255 Starts to add Qt target; resolves many build warnings. 2020-05-30 00:37:06 -04:00
8272 Adds a Qt timer class. Precision seems to be 'acceptable'. 2020-05-31 23:39:08 -04:00
8530 Ensures no double definition of NDEBUG. 2021-03-07 12:52:54 -05:00
9918 Correct no-interrupt signal. 2021-06-04 22:38:07 -04:00
68901 Switches to correct non-value sentinel. 2021-04-20 21:56:58 -04:00
AppleClock Establishes valid initial BRAM. 2021-09-10 19:56:20 -04:00
AudioToggle Starts to add Qt target; resolves many build warnings. 2020-05-30 00:37:06 -04:00
AY38910 Adds SZX support. 2021-04-26 20:47:28 -04:00
DiskII Walk back slightly. 2021-10-14 18:02:58 -07:00
KonamiSCC Starts to add Qt target; resolves many build warnings. 2020-05-30 00:37:06 -04:00
OPx Factors out shift by 7. 2020-05-10 13:57:50 -04:00
Serial Retain delegate bit length for non-self-clocked data. 2021-11-24 16:15:27 -05:00
SN76489 Further doubles down on construction syntax for type conversions. 2020-05-09 23:00:39 -04:00