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244 lines
8.2 KiB
C++
244 lines
8.2 KiB
C++
//
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// Decoder.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 01/01/21.
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// Copyright © 2021 Thomas Harte. All rights reserved.
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//
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#pragma once
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#include "Instruction.hpp"
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#include "Model.hpp"
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#include <cstddef>
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#include <utility>
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namespace InstructionSet::x86 {
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/*!
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Implements Intel x86 instruction decoding.
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This is an experimental implementation; it has not yet undergone significant testing.
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*/
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template <Model model> class Decoder {
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public:
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using InstructionT = Instruction<is_32bit(model)>;
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/*!
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@returns an @c Instruction plus a size; a positive size indicates successful decoding of
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an instruction that was that many bytes long in total; a negative size specifies the [negatived]
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minimum number of further bytes the caller should ideally collect before calling again. The
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caller is free to call with fewer, but may not get a decoded instruction in response, and the
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decoder may still not be able to complete decoding even if given that number of bytes.
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Successful decoding is defined to mean that all decoding steps are complete. The output
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may still be an illegal instruction (indicated by Operation::Invalid), if the byte sequence
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supplied cannot form a valid instruction.
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@discussion although instructions also contain an indicator of their length, on chips prior
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to the 80286 there is no limit to potential instruction length.
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The 80286 and 80386 have instruction length limits of 10 and 15 bytes respectively, so
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cannot overflow the field.
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*/
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std::pair<int, InstructionT> decode(const uint8_t *source, std::size_t length);
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/*!
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Enables or disables 32-bit protected mode. Meaningful only if the @c Model supports it.
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*/
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void set_32bit_protected_mode(bool);
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private:
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enum class Phase {
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/// Captures all prefixes and continues until an instruction byte is encountered.
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Instruction,
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/// Having encountered a 0x0f first instruction byte, waits for the next byte fully to determine the instruction.
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InstructionPageF,
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/// Receives a ModRegRM byte and either populates the source_ and dest_ fields appropriately
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/// or completes decoding of the instruction, as per the instruction format.
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ModRegRM,
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/// Awaits n 80386+-style scale-index-base byte ('SIB'), indicating the form of indirect addressing.
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ScaleIndexBase,
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/// Waits for sufficiently many bytes to pass for the required displacement and operand to be captured.
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/// Cf. displacement_size_ and operand_size_.
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DisplacementOrOperand,
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/// Forms and returns an Instruction, and resets parsing state.
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ReadyToPost
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} phase_ = Phase::Instruction;
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/// During the ModRegRM phase, format dictates interpretation of the ModRegRM byte.
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///
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/// During the ReadyToPost phase, format determines how transiently-recorded fields
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/// are packaged into an Instruction.
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enum class ModRegRMFormat: uint8_t {
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// Parse the ModRegRM for mode, register and register/memory fields
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// and populate the source_ and destination_ fields appropriately.
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MemReg_Reg,
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Reg_MemReg,
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// Parse for mode and register/memory fields, populating both
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// source_ and destination_ fields with the single register/memory result.
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MemRegSingleOperand,
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// Parse for mode and register/memory fields, populating both
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// the destination_ field with the result and setting source_ to Immediate.
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MemRegMOV,
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// Parse for mode and register/memory fields, populating the
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// source_ field with the result. Fills destination_ with a segment
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// register based on the reg field.
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Seg_MemReg,
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MemReg_Seg,
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//
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// 'Group 1'
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//
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// Parse for mode and register/memory fields, populating the
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// destination_ field with the result. Use the 'register' field
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// to pick an operation from the ADD/OR/ADC/SBB/AND/SUB/XOR/CMP group and
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// waits for an operand equal to the operation size.
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MemRegADD_to_CMP,
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// Acts exactly as MemRegADD_to_CMP but the operand is fixed in size
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// at a single byte, which is sign extended to the operation size.
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MemRegADD_to_CMP_SignExtend,
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//
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// 'Group 2'
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//
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// Parse for mode and register/memory fields, populating the
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// destination_ field with the result. Use the 'register' field
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// to pick an operation from the ROL/ROR/RCL/RCR/SAL/SHR/SAR group.
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MemRegROL_to_SAR,
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//
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// 'Group 3'
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//
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// Parse for mode and register/memory fields, populating both
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// source_ and destination_ fields with the result. Use the 'register'
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// field to pick an operation from the TEST/NOT/NEG/MUL/IMUL/DIV/IDIV group.
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MemRegTEST_to_IDIV,
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//
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// 'Group 4'
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//
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// Parse for mode and register/memory fields, populating the
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// source_ and destination_ fields with the result. Uses the
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// 'register' field to pick INC or DEC.
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MemRegINC_DEC,
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//
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// 'Group 5'
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//
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// Parse for mode and register/memory fields, populating the
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// source_ and destination_ fields with the result. Uses the
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// 'register' field to pick from INC/DEC/CALL/JMP/PUSH, altering
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// the source to ::Immediate and setting an operand size if necessary.
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MemRegINC_to_PUSH,
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//
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// 'Group 6'
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//
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// Parse for mode and register/memory field, populating both source_
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// and destination_ fields with the result. Uses the 'register' field
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// to pick from SLDT/STR/LLDT/LTR/VERR/VERW.
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MemRegSLDT_to_VERW,
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//
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// 'Group 7'
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//
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// Parse for mode and register/memory field, populating both source_
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// and destination_ fields with the result. Uses the 'register' field
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// to pick from SGDT/LGDT/SMSW/LMSW.
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MemRegSGDT_to_LMSW,
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//
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// 'Group 8'
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//
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// Parse for mode and register/memory field, populating destination,
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// and prepare to read a single byte as source.
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MemRegBT_to_BTC,
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} modregrm_format_ = ModRegRMFormat::MemReg_Reg;
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// Ephemeral decoding state.
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Operation operation_ = Operation::Invalid;
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int consumed_ = 0, operand_bytes_ = 0;
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// Source and destination locations.
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Source source_ = Source::None;
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Source destination_ = Source::None;
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// Immediate fields.
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int32_t displacement_ = 0;
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uint32_t operand_ = 0;
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uint64_t inward_data_ = 0;
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int next_inward_data_shift_ = 0;
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// Indirection style.
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ScaleIndexBase sib_;
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// Facts about the instruction.
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DataSize displacement_size_ = DataSize::None; // i.e. size of in-stream displacement, if any.
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DataSize operand_size_ = DataSize::None; // i.e. size of in-stream operand, if any.
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DataSize operation_size_ = DataSize::None; // i.e. size of data manipulated by the operation.
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bool sign_extend_displacement_ = true; // If set then sign extend any displacement up to the address
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// size; otherwise it'll be zero-padded.
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bool sign_extend_operand_ = false; // If set then sign extend the operand up to the operation size;
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// otherwise it'll be zero-padded.
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// Prefix capture fields.
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Repetition repetition_ = Repetition::None;
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bool lock_ = false;
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Source segment_override_ = Source::None;
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// 32-bit/16-bit selection.
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AddressSize default_address_size_ = AddressSize::b16;
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DataSize default_data_size_ = DataSize::Word;
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AddressSize address_size_ = AddressSize::b16;
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DataSize data_size_ = DataSize::Word;
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/// Resets size capture and all fields with default values.
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void reset_parsing() {
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consumed_ = operand_bytes_ = 0;
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displacement_size_ = operand_size_ = operation_size_ = DataSize::None;
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displacement_ = operand_ = 0;
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lock_ = false;
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address_size_ = default_address_size_;
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data_size_ = default_data_size_;
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segment_override_ = Source::None;
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repetition_ = Repetition::None;
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phase_ = Phase::Instruction;
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source_ = destination_ = Source::None;
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sib_ = ScaleIndexBase();
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next_inward_data_shift_ = 0;
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inward_data_ = 0;
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sign_extend_operand_ = false;
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sign_extend_displacement_ = true;
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}
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};
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// This is a temporary measure; for reasons as-yet unknown, GCC isn't picking up the
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// explicit instantiations of the template above at link time, even though is is
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// unambiguously building and linking in Decoder.cpp.
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//
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// So here's a thin non-templated shim to unblock initial PC Compatible development.
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class Decoder8086 {
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public:
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std::pair<int, Instruction<false>> decode(const uint8_t *source, std::size_t length);
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private:
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Decoder<Model::i8086> decoder;
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};
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}
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