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mirror of https://github.com/TomHarte/CLK.git synced 2024-11-30 04:50:08 +00:00
CLK/Processors
Thomas Harte db03b03276 Corrects [AND/OR/EOR].bw Dn, -(An) to decrement destination.
It was previously doing a predecrement on the internal source address, which is unused. This fixes at least Dan Dare III and Silkworm.
2019-11-09 11:25:23 -05:00
..
6502 Genericises RegisterPair. 2019-03-09 21:16:11 -05:00
68000 Corrects [AND/OR/EOR].bw Dn, -(An) to decrement destination. 2019-11-09 11:25:23 -05:00
Z80 Expands size of storage in Cycles/HalfCycles; adjusts widely to compensate. 2019-10-29 22:36:29 -04:00
AllRAMProcessor.cpp
AllRAMProcessor.hpp
RegisterSizes.hpp Embraces a more communicative 68000 bus. 2019-03-10 17:27:34 -04:00