mirror of
https://github.com/TomHarte/CLK.git
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293 lines
8.7 KiB
C++
293 lines
8.7 KiB
C++
//
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// Status.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 25/02/2024.
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// Copyright © 2024 Thomas Harte. All rights reserved.
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//
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#pragma once
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#include "OperationMapper.hpp"
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#include <array>
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#include <cstdint>
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namespace InstructionSet::ARM {
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namespace ConditionCode {
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static constexpr uint32_t Negative = 1u << 31;
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static constexpr uint32_t Zero = 1u << 30;
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static constexpr uint32_t Carry = 1u << 29;
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static constexpr uint32_t Overflow = 1u << 28;
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static constexpr uint32_t IRQDisable = 1u << 27;
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static constexpr uint32_t FIQDisable = 1u << 26;
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static constexpr uint32_t Mode = (1u << 1) | (1u << 0);
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static constexpr uint32_t Address = FIQDisable - Mode - 1;
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}
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enum class Mode {
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User = 0b00,
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FIQ = 0b01,
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IRQ = 0b10,
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Supervisor = 0b11,
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};
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/// Combines the ARM registers and status flags into a single whole, given that the architecture
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/// doesn't have the same degree of separation as others.
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///
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/// The PC contained here is always taken to be **the address of the current instruction + 4**,
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/// i.e. whatever should be executed next, disregarding pipeline differences.
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///
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/// Appropriate prefetch offsets are left to other code to handle.
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/// This is to try to keep this structure independent of a specific ARM implementation.
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struct Registers {
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public:
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/// Sets the N and Z flags according to the value of @c result.
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void set_nz(uint32_t value) {
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zero_result_ = negative_flag_ = value;
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}
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/// Sets C if @c value is non-zero; resets it otherwise.
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void set_c(uint32_t value) {
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carry_flag_ = value;
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}
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/// @returns @c 1 if carry is set; @c 0 otherwise.
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uint32_t c() const {
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return carry_flag_ ? 1 : 0;
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}
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/// Sets V if the highest bit of @c value is set; resets it otherwise.
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void set_v(uint32_t value) {
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overflow_flag_ = value;
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}
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/// @returns The current status bits, separate from the PC — mode, NVCZ and the two interrupt flags.
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uint32_t status() const {
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return
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uint32_t(mode_) |
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(negative_flag_ & ConditionCode::Negative) |
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(zero_result_ ? 0 : ConditionCode::Zero) |
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(carry_flag_ ? ConditionCode::Carry : 0) |
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((overflow_flag_ >> 3) & ConditionCode::Overflow) |
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interrupt_flags_;
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}
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/// @returns The full PC + status bits.
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uint32_t pc_status(uint32_t offset) const {
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return
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((active_[15] + offset) & ConditionCode::Address) |
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status();
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}
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/// Sets status bits only, subject to mode.
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void set_status(uint32_t status) {
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// ... in user mode the other flags (I, F, M1, M0) are protected from direct change
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// but in non-user modes these will also be affected, accepting copies of bits 27, 26,
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// 1 and 0 of the result respectively.
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negative_flag_ = status;
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overflow_flag_ = status << 3;
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carry_flag_ = status & ConditionCode::Carry;
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zero_result_ = ~status & ConditionCode::Zero;
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if(mode_ != Mode::User) {
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set_mode(Mode(status & 3));
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interrupt_flags_ = status & (ConditionCode::IRQDisable | ConditionCode::FIQDisable);
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}
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}
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/// @returns The current mode.
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Mode mode() const {
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return mode_;
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}
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/// Sets a new PC.
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void set_pc(uint32_t value) {
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active_[15] = value & ConditionCode::Address;
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}
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/// @returns The stored PC plus @c offset limited to 26 bits.
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uint32_t pc(uint32_t offset) const {
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return (active_[15] + offset) & ConditionCode::Address;
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}
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// MARK: - Exceptions.
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enum class Exception {
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/// Reset line went from high to low.
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Reset = 0x00,
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/// Either an undefined instruction or a coprocessor instruction for which no coprocessor was found.
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UndefinedInstruction = 0x04,
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/// Code executed a software interrupt.
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SoftwareInterrupt = 0x08,
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/// The memory subsystem indicated an abort during prefetch and that instruction has now come to the head of the queue.
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PrefetchAbort = 0x0c,
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/// The memory subsystem indicated an abort during an instruction; if it is an LDR or STR then this should be signalled
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/// before any instruction execution. If it was an LDM then loading stops upon a data abort but both an LDM and STM
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/// otherwise complete, including pointer writeback.
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DataAbort = 0x10,
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/// The first data transfer attempted within an instruction was above address 0x3ff'ffff.
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Address = 0x14,
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/// The IRQ line was low at the end of an instruction and ConditionCode::IRQDisable was not set.
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IRQ = 0x18,
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/// The FIQ went low at least one cycle ago and ConditionCode::FIQDisable was not set.
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FIQ = 0x1c,
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};
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/// Updates the program counter, interupt flags and link register if applicable to begin @c exception.
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template <Exception type>
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void exception() {
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interrupt_flags_ |= ConditionCode::IRQDisable;
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if constexpr (type == Exception::Reset || type == Exception::FIQ) {
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interrupt_flags_ |= ConditionCode::FIQDisable;
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}
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switch(type) {
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case Exception::IRQ:
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set_mode(Mode::IRQ);
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active_[14] = pc(8);
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break;
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case Exception::FIQ:
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set_mode(Mode::FIQ);
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active_[14] = pc(8);
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break;
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default:
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set_mode(Mode::Supervisor);
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active_[14] = pc(4);
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break;
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}
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set_pc(uint32_t(type));
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}
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// MARK: - Condition tests.
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/// @returns @c true if @c condition tests as true; @c false otherwise.
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bool test(Condition condition) {
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const auto ne = [&]() -> bool {
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return zero_result_;
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};
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const auto cs = [&]() -> bool {
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return carry_flag_;
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};
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const auto mi = [&]() -> bool {
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return negative_flag_ & ConditionCode::Negative;
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};
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const auto vs = [&]() -> bool {
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return overflow_flag_ & ConditionCode::Negative;
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};
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const auto hi = [&]() -> bool {
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return carry_flag_ && zero_result_;
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};
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const auto lt = [&]() -> bool {
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return (negative_flag_ ^ overflow_flag_) & ConditionCode::Negative;
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};
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const auto le = [&]() -> bool {
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return !zero_result_ || lt();
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};
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switch(condition) {
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case Condition::EQ: return !ne();
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case Condition::NE: return ne();
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case Condition::CS: return cs();
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case Condition::CC: return !cs();
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case Condition::MI: return mi();
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case Condition::PL: return !mi();
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case Condition::VS: return vs();
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case Condition::VC: return !vs();
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case Condition::HI: return hi();
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case Condition::LS: return !hi();
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case Condition::GE: return !lt();
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case Condition::LT: return lt();
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case Condition::GT: return !le();
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case Condition::LE: return le();
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case Condition::AL: return true;
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case Condition::NV: return false;
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}
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}
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/// Sets current execution mode.
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void set_mode(Mode target_mode) {
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if(mode_ == target_mode) {
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return;
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}
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// For outgoing modes other than FIQ, only save the final two registers for now;
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// if the incoming mode is FIQ then the other five will be saved in the next switch.
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switch(mode_) {
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case Mode::FIQ:
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std::copy(active_.begin() + 8, active_.begin() + 15, fiq_registers_.begin());
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break;
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case Mode::User:
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std::copy(active_.begin() + 13, active_.begin() + 15, user_registers_.begin() + 5);
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break;
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case Mode::Supervisor:
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std::copy(active_.begin() + 13, active_.begin() + 15, supervisor_registers_.begin());
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break;
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case Mode::IRQ:
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std::copy(active_.begin() + 13, active_.begin() + 15, irq_registers_.begin());
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break;
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}
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// For all modes except FIQ: restore the final two registers to their appropriate values.
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// For FIQ: save an additional five, then overwrite seven.
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switch(target_mode) {
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case Mode::FIQ:
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std::copy(active_.begin() + 8, active_.begin() + 13, user_registers_.begin());
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std::copy(fiq_registers_.begin(), fiq_registers_.end(), active_.begin() + 8);
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break;
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case Mode::User:
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std::copy(user_registers_.begin() + 5, user_registers_.end(), active_.begin() + 13);
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break;
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case Mode::Supervisor:
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std::copy(supervisor_registers_.begin(), supervisor_registers_.end(), active_.begin() + 13);
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break;
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case Mode::IRQ:
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std::copy(irq_registers_.begin(), irq_registers_.end(), active_.begin() + 13);
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break;
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}
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// If FIQ is outgoing then there's another five registers to restore.
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if(mode_ == Mode::FIQ) {
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std::copy(user_registers_.begin(), user_registers_.begin() + 5, active_.begin() + 8);
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}
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mode_ = target_mode;
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}
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uint32_t &operator[](size_t offset) {
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return active_[offset];
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}
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uint32_t operator[](size_t offset) const {
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return active_[offset];
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}
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private:
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Mode mode_ = Mode::Supervisor;
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uint32_t zero_result_ = 1;
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uint32_t negative_flag_ = 0;
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uint32_t interrupt_flags_ = ConditionCode::IRQDisable | ConditionCode::FIQDisable;
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uint32_t carry_flag_ = 0;
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uint32_t overflow_flag_ = 0;
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// Various shadow registers.
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std::array<uint32_t, 7> user_registers_{};
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std::array<uint32_t, 7> fiq_registers_{};
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std::array<uint32_t, 2> irq_registers_{};
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std::array<uint32_t, 2> supervisor_registers_{};
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// The active register set.
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std::array<uint32_t, 16> active_{};
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};
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}
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