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1210 lines
33 KiB
C++
1210 lines
33 KiB
C++
//
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// PerformImplementation.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 28/04/2022.
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// Copyright © 2022 Thomas Harte. All rights reserved.
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//
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#ifndef InstructionSets_M68k_PerformImplementation_h
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#define InstructionSets_M68k_PerformImplementation_h
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#include "../ExceptionVectors.hpp"
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#include <cassert>
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#include <cmath>
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namespace InstructionSet {
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namespace M68k {
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#define u_extend16(x) uint32_t(int16_t(x))
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#define s_extend16(x) int32_t(int16_t(x))
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template <
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Model model,
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typename FlowController,
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Operation operation = Operation::Undefined
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> void perform(Preinstruction instruction, CPU::SlicedInt32 &src, CPU::SlicedInt32 &dest, Status &status, FlowController &flow_controller) {
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#define sub_overflow() ((result ^ destination) & (destination ^ source))
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#define add_overflow() ((result ^ destination) & ~(destination ^ source))
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switch((operation != Operation::Undefined) ? operation : instruction.operation) {
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/*
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ABCD adds the lowest bytes from the source and destination using BCD arithmetic,
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obeying the extend flag.
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*/
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case Operation::ABCD: {
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// Pull out the two halves, for simplicity.
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const uint8_t source = src.b;
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const uint8_t destination = dest.b;
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const int extend = (status.extend_flag ? 1 : 0);
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// Perform the BCD add by evaluating the two nibbles separately.
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const int unadjusted_result = destination + source + extend;
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int result = (destination & 0xf) + (source & 0xf) + extend;
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result +=
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(destination & 0xf0) +
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(source & 0xf0) +
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(((9 - result) >> 4) & 0x06); // i.e. ((result > 0x09) ? 0x06 : 0x00)
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result += ((0x9f - result) >> 4) & 0x60; // i.e. ((result > 0x9f) ? 0x60 : 0x00)
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// Set all flags essentially as if this were normal addition.
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status.zero_result |= result & 0xff;
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status.extend_flag = status.carry_flag = uint_fast32_t(result & ~0xff);
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status.negative_flag = result & 0x80;
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status.overflow_flag = ~unadjusted_result & result & 0x80;
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// Store the result.
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dest.b = uint8_t(result);
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} break;
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#define addop(a, b, x) a + b + (x ? 1 : 0)
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#define subop(a, b, x) a - b - (x ? 1 : 0)
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#define z_set(a, b) a = b
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#define z_or(a, b) a |= b
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#define addsubb(a, b, op, overflow, x, zero_op) \
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const int source = a; \
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const int destination = b; \
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const auto result = op(destination, source, x); \
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\
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b = uint8_t(result); \
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zero_op(status.zero_result, b); \
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status.extend_flag = status.carry_flag = uint_fast32_t(result & ~0xff); \
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status.negative_flag = result & 0x80; \
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status.overflow_flag = overflow() & 0x80;
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#define addsubw(a, b, op, overflow, x, zero_op) \
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const int source = a; \
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const int destination = b; \
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const auto result = op(destination, source, x); \
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\
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b = uint16_t(result); \
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zero_op(status.zero_result, b); \
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status.extend_flag = status.carry_flag = uint_fast32_t(result & ~0xffff); \
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status.negative_flag = result & 0x8000; \
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status.overflow_flag = overflow() & 0x8000;
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#define addsubl(a, b, op, overflow, x, zero_op) \
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const uint64_t source = a; \
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const uint64_t destination = b; \
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const auto result = op(destination, source, x); \
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\
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b = uint32_t(result); \
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zero_op(status.zero_result, b); \
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status.extend_flag = status.carry_flag = uint_fast32_t(result >> 32); \
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status.negative_flag = result & 0x80000000; \
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status.overflow_flag = overflow() & 0x80000000;
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#define addb(a, b, x, z) addsubb(a, b, addop, add_overflow, x, z)
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#define subb(a, b, x, z) addsubb(a, b, subop, sub_overflow, x, z)
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#define addw(a, b, x, z) addsubw(a, b, addop, add_overflow, x, z)
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#define subw(a, b, x, z) addsubw(a, b, subop, sub_overflow, x, z)
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#define addl(a, b, x, z) addsubl(a, b, addop, add_overflow, x, z)
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#define subl(a, b, x, z) addsubl(a, b, subop, sub_overflow, x, z)
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#define no_extend(op, a, b) op(a, b, 0, z_set)
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#define extend(op, a, b) op(a, b, status.extend_flag, z_or)
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// ADD and ADDA add two quantities, the latter sign extending and without setting any flags;
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// ADDQ and SUBQ act as ADD and SUB, but taking the second argument from the instruction code.
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case Operation::ADDb: {
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no_extend( addb,
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src.b,
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dest.b);
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} break;
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case Operation::ADDXb: {
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extend( addb,
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src.b,
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dest.b);
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} break;
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case Operation::ADDw: {
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no_extend( addw,
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src.w,
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dest.w);
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} break;
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case Operation::ADDXw: {
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extend( addw,
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src.w,
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dest.w);
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} break;
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case Operation::ADDl: {
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no_extend( addl,
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src.l,
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dest.l);
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} break;
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case Operation::ADDXl: {
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extend( addl,
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src.l,
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dest.l);
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} break;
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case Operation::SUBb: {
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no_extend( subb,
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src.b,
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dest.b);
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} break;
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case Operation::SUBXb: {
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extend( subb,
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src.b,
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dest.b);
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} break;
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case Operation::SUBw: {
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no_extend( subw,
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src.w,
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dest.w);
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} break;
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case Operation::SUBXw: {
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extend( subw,
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src.w,
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dest.w);
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} break;
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case Operation::SUBl: {
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no_extend( subl,
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src.l,
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dest.l);
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} break;
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case Operation::SUBXl: {
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extend( subl,
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src.l,
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dest.l);
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} break;
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#undef addl
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#undef addw
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#undef addb
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#undef subl
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#undef subw
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#undef subb
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#undef addsubl
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#undef addsubw
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#undef addsubb
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#undef z_set
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#undef z_or
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#undef no_extend
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#undef extend
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#undef addop
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#undef subop
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case Operation::ADDAw:
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dest.l += u_extend16(src.w);
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break;
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case Operation::ADDAl:
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dest.l += src.l;
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break;
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case Operation::SUBAw:
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dest.l -= u_extend16(src.w);
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break;
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case Operation::SUBAl:
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dest.l -= src.l;
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break;
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#define get_mask() \
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const uint32_t mask_size = (instruction.mode<1>() == AddressingMode::DataRegisterDirect) ? 31 : 7; \
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const uint32_t bit_position = src.l & mask_size; \
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const uint32_t bit_mask = 1 << bit_position
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// BTST/BCLR/etc: modulo for the mask depends on whether memory or a data register is the target.
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case Operation::BTST: {
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get_mask();
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status.zero_result = dest.l & bit_mask;
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} break;
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case Operation::BCLR: {
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get_mask();
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status.zero_result = dest.l & bit_mask;
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dest.l &= ~bit_mask;
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flow_controller.did_bit_op(bit_position);
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} break;
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case Operation::BCHG: {
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get_mask();
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status.zero_result = dest.l & bit_mask;
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dest.l ^= bit_mask;
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flow_controller.did_bit_op(bit_position);
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} break;
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case Operation::BSET: {
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get_mask();
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status.zero_result = dest.l & bit_mask;
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dest.l |= bit_mask;
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flow_controller.did_bit_op(bit_position);
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} break;
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#undef get_mask
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case Operation::Bccb:
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flow_controller.template complete_bcc<int8_t>(
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status.evaluate_condition(instruction.condition()),
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src.b);
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break;
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case Operation::Bccw:
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flow_controller.template complete_bcc<int16_t>(
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status.evaluate_condition(instruction.condition()),
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src.w);
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break;
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case Operation::Bccl:
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flow_controller.template complete_bcc<int32_t>(
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status.evaluate_condition(instruction.condition()),
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src.l);
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break;
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case Operation::BSRb:
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flow_controller.bsr(int8_t(src.b) + 2);
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break;
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case Operation::BSRw:
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flow_controller.bsr(int16_t(src.w) + 2);
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break;
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case Operation::BSRl:
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flow_controller.bsr(src.l + 2);
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break;
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case Operation::DBcc: {
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const bool matched_condition = status.evaluate_condition(instruction.condition());
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bool overflowed = false;
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// Classify the dbcc.
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if(!matched_condition) {
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-- src.w;
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overflowed = src.w == 0xffff;
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}
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// Take the branch.
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flow_controller.complete_dbcc(
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matched_condition,
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overflowed,
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int16_t(dest.w));
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} break;
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case Operation::Scc:
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src.b = status.evaluate_condition(instruction.condition()) ? 0xff : 0x00;
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break;
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/*
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CLRs: store 0 to the destination, set the zero flag, and clear
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negative, overflow and carry.
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*/
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case Operation::CLRb:
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src.b = 0;
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status.negative_flag = status.overflow_flag = status.carry_flag = status.zero_result = 0;
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break;
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case Operation::CLRw:
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src.w = 0;
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status.negative_flag = status.overflow_flag = status.carry_flag = status.zero_result = 0;
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break;
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case Operation::CLRl:
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src.l = 0;
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status.negative_flag = status.overflow_flag = status.carry_flag = status.zero_result = 0;
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break;
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/*
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CMP.b, CMP.l and CMP.w: sets the condition flags (other than extend) based on a subtraction
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of the source from the destination; the result of the subtraction is not stored.
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*/
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case Operation::CMPb: {
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const uint8_t source = src.b;
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const uint8_t destination = dest.b;
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const int result = destination - source;
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status.zero_result = result & 0xff;
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status.carry_flag = Status::FlagT(result & ~0xff);
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status.negative_flag = result & 0x80;
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status.overflow_flag = sub_overflow() & 0x80;
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} break;
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case Operation::CMPw: {
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const uint16_t source = src.w;
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const uint16_t destination = dest.w;
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const int result = destination - source;
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status.zero_result = result & 0xffff;
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status.carry_flag = Status::FlagT(result & ~0xffff);
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status.negative_flag = result & 0x8000;
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status.overflow_flag = sub_overflow() & 0x8000;
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} break;
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case Operation::CMPAw: {
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const auto source = uint64_t(u_extend16(src.w));
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const uint64_t destination = dest.l;
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const auto result = destination - source;
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status.zero_result = uint32_t(result);
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status.carry_flag = result >> 32;
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status.negative_flag = result & 0x80000000;
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status.overflow_flag = sub_overflow() & 0x80000000;
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} break;
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// TODO: is there any benefit to keeping both of these?
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case Operation::CMPAl:
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case Operation::CMPl: {
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const auto source = uint64_t(src.l);
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const auto destination = uint64_t(dest.l);
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const auto result = destination - source;
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status.zero_result = uint32_t(result);
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status.carry_flag = result >> 32;
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status.negative_flag = result & 0x80000000;
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status.overflow_flag = sub_overflow() & 0x80000000;
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} break;
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// JMP: copies EA(0) to the program counter.
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case Operation::JMP:
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flow_controller.jmp(src.l);
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break;
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// JSR: jump to EA(0), pushing the current PC to the stack.
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case Operation::JSR:
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flow_controller.jsr(src.l);
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break;
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/*
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MOVE.b, MOVE.l and MOVE.w: move the least significant byte or word, or the entire long word,
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and set negative, zero, overflow and carry as appropriate.
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*/
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case Operation::MOVEb:
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status.zero_result = dest.b = src.b;
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status.negative_flag = status.zero_result & 0x80;
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status.overflow_flag = status.carry_flag = 0;
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break;
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case Operation::MOVEw:
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status.zero_result = dest.w = src.w;
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status.negative_flag = status.zero_result & 0x8000;
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status.overflow_flag = status.carry_flag = 0;
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break;
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case Operation::MOVEl:
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status.zero_result = dest.l = src.l;
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status.negative_flag = status.zero_result & 0x80000000;
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status.overflow_flag = status.carry_flag = 0;
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break;
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/*
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MOVEA.l: move the entire long word;
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MOVEA.w: move the least significant word and sign extend it.
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Neither sets any flags.
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*/
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case Operation::MOVEAw:
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dest.l = u_extend16(src.w);
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break;
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case Operation::MOVEAl:
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dest.l = src.l;
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break;
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case Operation::LEA:
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dest.l = src.l;
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break;
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case Operation::PEA:
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flow_controller.pea(src.l);
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break;
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/*
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Status word moves and manipulations.
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*/
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case Operation::MOVEtoSR:
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status.set_status(src.w);
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flow_controller.did_update_status();
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break;
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case Operation::MOVEfromSR:
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src.w = status.status();
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break;
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case Operation::MOVEtoCCR:
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status.set_ccr(src.w);
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break;
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case Operation::MOVEtoUSP:
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flow_controller.move_to_usp(src.l);
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break;
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case Operation::MOVEfromUSP:
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flow_controller.move_from_usp(src.l);
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break;
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case Operation::EXTbtow:
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src.w = uint16_t(int8_t(src.b));
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status.overflow_flag = status.carry_flag = 0;
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status.zero_result = src.w;
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status.negative_flag = status.zero_result & 0x8000;
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break;
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case Operation::EXTwtol:
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src.l = u_extend16(src.w);
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status.overflow_flag = status.carry_flag = 0;
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status.zero_result = src.l;
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status.negative_flag = status.zero_result & 0x80000000;
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break;
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#define and_op(a, b) a &= b
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#define or_op(a, b) a |= b
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#define eor_op(a, b) a ^= b
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#define apply(op, func) { \
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auto sr = status.status(); \
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op(sr, src.w); \
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func(sr); \
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}
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#define set_status(x) status.set_status(x); flow_controller.did_update_status()
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#define set_ccr(x) status.set_ccr(x)
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#define apply_op_sr(op) apply(op, set_status)
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#define apply_op_ccr(op) apply(op, set_ccr)
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case Operation::ANDItoSR: apply_op_sr(and_op); break;
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case Operation::EORItoSR: apply_op_sr(eor_op); break;
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case Operation::ORItoSR: apply_op_sr(or_op); break;
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case Operation::ANDItoCCR: apply_op_ccr(and_op); break;
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case Operation::EORItoCCR: apply_op_ccr(eor_op); break;
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case Operation::ORItoCCR: apply_op_ccr(or_op); break;
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#undef apply_op_ccr
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#undef apply_op_sr
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#undef set_ccr
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#undef set_status
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#undef apply
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#undef eor_op
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#undef or_op
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#undef and_op
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/*
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Multiplications.
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*/
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case Operation::MULU:
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dest.l = dest.w * src.w;
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status.carry_flag = status.overflow_flag = 0;
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status.zero_result = dest.l;
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status.negative_flag = status.zero_result & 0x80000000;
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flow_controller.did_mulu(src.w);
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break;
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case Operation::MULS:
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dest.l =
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u_extend16(dest.w) * u_extend16(src.w);
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status.carry_flag = status.overflow_flag = 0;
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status.zero_result = dest.l;
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status.negative_flag = status.zero_result & 0x80000000;
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flow_controller.did_muls(src.w);
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break;
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/*
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Divisions.
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*/
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#define announce_divide_by_zero() \
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status.negative_flag = status.overflow_flag = 0; \
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status.zero_result = 1; \
|
|
flow_controller.raise_exception(Exception::IntegerDivideByZero)
|
|
|
|
case Operation::DIVU: {
|
|
status.carry_flag = 0;
|
|
|
|
// An attempt to divide by zero schedules an exception.
|
|
if(!src.w) {
|
|
// Schedule a divide-by-zero exception.
|
|
announce_divide_by_zero();
|
|
return;
|
|
}
|
|
|
|
uint32_t dividend = dest.l;
|
|
uint32_t divisor = src.w;
|
|
const auto quotient = dividend / divisor;
|
|
|
|
// If overflow would occur, appropriate flags are set and the result is not written back.
|
|
if(quotient > 65535) {
|
|
status.overflow_flag = status.zero_result = status.negative_flag = 1;
|
|
flow_controller.template did_divu<true>(dividend, divisor);
|
|
return;
|
|
}
|
|
|
|
const uint16_t remainder = uint16_t(dividend % divisor);
|
|
dest.l = uint32_t((remainder << 16) | uint16_t(quotient));
|
|
|
|
status.overflow_flag = 0;
|
|
status.zero_result = quotient;
|
|
status.negative_flag = status.zero_result & 0x8000;
|
|
flow_controller.template did_divu<false>(dividend, divisor);
|
|
} break;
|
|
|
|
case Operation::DIVS: {
|
|
status.carry_flag = 0;
|
|
|
|
// An attempt to divide by zero schedules an exception.
|
|
if(!src.w) {
|
|
// Schedule a divide-by-zero exception.
|
|
announce_divide_by_zero();
|
|
break;
|
|
}
|
|
|
|
const int32_t signed_dividend = int32_t(dest.l);
|
|
const int32_t signed_divisor = s_extend16(src.w);
|
|
const auto result_sign =
|
|
( (0 <= signed_dividend) - (signed_dividend < 0) ) *
|
|
( (0 <= signed_divisor) - (signed_divisor < 0) );
|
|
|
|
const uint32_t dividend = uint32_t(std::abs(signed_dividend));
|
|
const uint32_t divisor = uint32_t(std::abs(signed_divisor));
|
|
|
|
int cycles_expended = 12; // Covers the nn nnn n to get beyond the sign test.
|
|
if(signed_dividend < 0) {
|
|
cycles_expended += 2; // An additional microycle applies if the dividend is negative.
|
|
}
|
|
|
|
// Check for overflow. If it exists, work here is already done.
|
|
const auto quotient = dividend / divisor;
|
|
if(quotient > 32767) {
|
|
status.overflow_flag = 1;
|
|
flow_controller.template did_divs<true>(signed_dividend, signed_divisor);
|
|
break;
|
|
}
|
|
|
|
const uint16_t remainder = uint16_t(signed_dividend % signed_divisor);
|
|
const int signed_quotient = result_sign*int(quotient);
|
|
dest.l = uint32_t((remainder << 16) | uint16_t(signed_quotient));
|
|
|
|
status.zero_result = Status::FlagT(signed_quotient);
|
|
status.negative_flag = status.zero_result & 0x8000;
|
|
status.overflow_flag = 0;
|
|
flow_controller.template did_divs<false>(signed_dividend, signed_divisor);
|
|
} break;
|
|
|
|
#undef announce_divide_by_zero
|
|
|
|
// TRAP, which is a nicer form of ILLEGAL.
|
|
case Operation::TRAP:
|
|
flow_controller.template raise_exception<false>(src.l + Exception::TrapBase);
|
|
break;
|
|
|
|
case Operation::TRAPV: {
|
|
if(status.overflow_flag) {
|
|
flow_controller.template raise_exception<false>(Exception::TRAPV);
|
|
}
|
|
} break;
|
|
|
|
case Operation::CHK: {
|
|
const bool is_under = s_extend16(dest.w) < 0;
|
|
const bool is_over = s_extend16(dest.w) > s_extend16(src.w);
|
|
|
|
status.overflow_flag = status.carry_flag = 0;
|
|
status.zero_result = dest.w;
|
|
|
|
// Test applied for N:
|
|
//
|
|
// if Dn < 0, set negative flag;
|
|
// otherwise, if Dn > <ea>, reset negative flag.
|
|
if(is_over) status.negative_flag = 0;
|
|
if(is_under) status.negative_flag = 1;
|
|
|
|
// No exception is the default course of action; deviate only if an
|
|
// exception is necessary.
|
|
flow_controller.did_chk(is_under, is_over);
|
|
if(is_under || is_over) {
|
|
flow_controller.template raise_exception<false>(Exception::CHK);
|
|
}
|
|
} break;
|
|
|
|
/*
|
|
NEGs: negatives the destination, setting the zero,
|
|
negative, overflow and carry flags appropriate, and extend.
|
|
|
|
NB: since the same logic as SUB is used to calculate overflow,
|
|
and SUB calculates `destination - source`, the NEGs deliberately
|
|
label 'source' and 'destination' differently from Motorola.
|
|
*/
|
|
case Operation::NEGb: {
|
|
const int destination = 0;
|
|
const int source = src.b;
|
|
const auto result = destination - source;
|
|
src.b = uint8_t(result);
|
|
|
|
status.zero_result = result & 0xff;
|
|
status.extend_flag = status.carry_flag = Status::FlagT(result & ~0xff);
|
|
status.negative_flag = result & 0x80;
|
|
status.overflow_flag = sub_overflow() & 0x80;
|
|
} break;
|
|
|
|
case Operation::NEGw: {
|
|
const int destination = 0;
|
|
const int source = src.w;
|
|
const auto result = destination - source;
|
|
src.w = uint16_t(result);
|
|
|
|
status.zero_result = result & 0xffff;
|
|
status.extend_flag = status.carry_flag = Status::FlagT(result & ~0xffff);
|
|
status.negative_flag = result & 0x8000;
|
|
status.overflow_flag = sub_overflow() & 0x8000;
|
|
} break;
|
|
|
|
case Operation::NEGl: {
|
|
const uint64_t destination = 0;
|
|
const uint64_t source = src.l;
|
|
const auto result = destination - source;
|
|
src.l = uint32_t(result);
|
|
|
|
status.zero_result = uint_fast32_t(result);
|
|
status.extend_flag = status.carry_flag = result >> 32;
|
|
status.negative_flag = result & 0x80000000;
|
|
status.overflow_flag = sub_overflow() & 0x80000000;
|
|
} break;
|
|
|
|
/*
|
|
NEGXs: NEG, with extend.
|
|
*/
|
|
case Operation::NEGXb: {
|
|
const int source = src.b;
|
|
const int destination = 0;
|
|
const auto result = destination - source - (status.extend_flag ? 1 : 0);
|
|
src.b = uint8_t(result);
|
|
|
|
status.zero_result |= result & 0xff;
|
|
status.extend_flag = status.carry_flag = Status::FlagT(result & ~0xff);
|
|
status.negative_flag = result & 0x80;
|
|
status.overflow_flag = sub_overflow() & 0x80;
|
|
} break;
|
|
|
|
case Operation::NEGXw: {
|
|
const int source = src.w;
|
|
const int destination = 0;
|
|
const auto result = destination - source - (status.extend_flag ? 1 : 0);
|
|
src.w = uint16_t(result);
|
|
|
|
status.zero_result |= result & 0xffff;
|
|
status.extend_flag = status.carry_flag = Status::FlagT(result & ~0xffff);
|
|
status.negative_flag = result & 0x8000;
|
|
status.overflow_flag = sub_overflow() & 0x8000;
|
|
} break;
|
|
|
|
case Operation::NEGXl: {
|
|
const uint64_t source = src.l;
|
|
const uint64_t destination = 0;
|
|
const auto result = destination - source - (status.extend_flag ? 1 : 0);
|
|
src.l = uint32_t(result);
|
|
|
|
status.zero_result |= uint_fast32_t(result);
|
|
status.extend_flag = status.carry_flag = result >> 32;
|
|
status.negative_flag = result & 0x80000000;
|
|
status.overflow_flag = sub_overflow() & 0x80000000;
|
|
} break;
|
|
|
|
/*
|
|
The no-op.
|
|
*/
|
|
case Operation::NOP: break;
|
|
|
|
/*
|
|
LINK and UNLINK help with stack frames, allowing a certain
|
|
amount of stack space to be allocated or deallocated.
|
|
*/
|
|
|
|
case Operation::LINKw:
|
|
flow_controller.link(instruction, int16_t(dest.w));
|
|
break;
|
|
|
|
case Operation::UNLINK:
|
|
flow_controller.unlink(src.l);
|
|
break;
|
|
|
|
/*
|
|
TAS: sets zero and negative depending on the current value of the destination,
|
|
and sets the high bit, using a specialised atomic bus cycle.
|
|
*/
|
|
|
|
case Operation::TAS:
|
|
flow_controller.tas(instruction, src.l);
|
|
break;
|
|
|
|
/*
|
|
Bitwise operators: AND, OR and EOR. All three clear the overflow and carry flags,
|
|
and set zero and negative appropriately.
|
|
*/
|
|
#define op_and(x, y) x &= y
|
|
#define op_or(x, y) x |= y
|
|
#define op_eor(x, y) x ^= y
|
|
|
|
#define bitwise(source, dest, sign_mask, operator) \
|
|
operator(dest, source); \
|
|
status.overflow_flag = status.carry_flag = 0; \
|
|
status.zero_result = dest; \
|
|
status.negative_flag = dest & sign_mask;
|
|
|
|
#define andx(source, dest, sign_mask) bitwise(source, dest, sign_mask, op_and)
|
|
#define eorx(source, dest, sign_mask) bitwise(source, dest, sign_mask, op_eor)
|
|
#define orx(source, dest, sign_mask) bitwise(source, dest, sign_mask, op_or)
|
|
|
|
#define op_bwl(name, op) \
|
|
case Operation::name##b: op(src.b, dest.b, 0x80); break; \
|
|
case Operation::name##w: op(src.w, dest.w, 0x8000); break; \
|
|
case Operation::name##l: op(src.l, dest.l, 0x80000000); break;
|
|
|
|
op_bwl(AND, andx);
|
|
op_bwl(EOR, eorx);
|
|
op_bwl(OR, orx);
|
|
|
|
#undef op_bwl
|
|
#undef orx
|
|
#undef eorx
|
|
#undef andx
|
|
#undef bitwise
|
|
#undef op_eor
|
|
#undef op_or
|
|
#undef op_and
|
|
|
|
// NOTs: take the logical inverse, affecting the negative and zero flags.
|
|
case Operation::NOTb:
|
|
src.b ^= 0xff;
|
|
status.zero_result = src.b;
|
|
status.negative_flag = status.zero_result & 0x80;
|
|
status.overflow_flag = status.carry_flag = 0;
|
|
break;
|
|
|
|
case Operation::NOTw:
|
|
src.w ^= 0xffff;
|
|
status.zero_result = src.w;
|
|
status.negative_flag = status.zero_result & 0x8000;
|
|
status.overflow_flag = status.carry_flag = 0;
|
|
break;
|
|
|
|
case Operation::NOTl:
|
|
src.l ^= 0xffffffff;
|
|
status.zero_result = src.l;
|
|
status.negative_flag = status.zero_result & 0x80000000;
|
|
status.overflow_flag = status.carry_flag = 0;
|
|
break;
|
|
|
|
#define sbcd(d) \
|
|
const int extend = (status.extend_flag ? 1 : 0); \
|
|
const int unadjusted_result = destination - source - extend; \
|
|
\
|
|
const int top = (destination & 0xf0) - (source & 0xf0) - (0x60 & (unadjusted_result >> 4)); \
|
|
\
|
|
int result = (destination & 0xf) - (source & 0xf) - extend; \
|
|
const int low_adjustment = 0x06 & (result >> 4); \
|
|
status.extend_flag = status.carry_flag = Status::FlagT( \
|
|
(unadjusted_result - low_adjustment) & 0x300 \
|
|
); \
|
|
result = result + top - low_adjustment; \
|
|
\
|
|
/* Store the result. */ \
|
|
d = uint8_t(result); \
|
|
\
|
|
/* Set all remaining flags essentially as if this were normal subtraction. */ \
|
|
status.zero_result |= d; \
|
|
status.negative_flag = result & 0x80; \
|
|
status.overflow_flag = unadjusted_result & ~result & 0x80; \
|
|
|
|
/*
|
|
SBCD subtracts the lowest byte of the source from that of the destination using
|
|
BCD arithmetic, obeying the extend flag.
|
|
*/
|
|
case Operation::SBCD: {
|
|
const uint8_t source = src.b;
|
|
const uint8_t destination = dest.b;
|
|
sbcd(dest.b);
|
|
} break;
|
|
|
|
/*
|
|
NBCD is like SBCD except that the result is 0 - source rather than
|
|
destination - source.
|
|
*/
|
|
case Operation::NBCD: {
|
|
const uint8_t source = src.b;
|
|
const uint8_t destination = 0;
|
|
sbcd(src.b);
|
|
} break;
|
|
|
|
#undef sbcd
|
|
|
|
// EXG and SWAP exchange/swap words or long words.
|
|
|
|
case Operation::EXG: {
|
|
const auto temporary = src.l;
|
|
src.l = dest.l;
|
|
dest.l = temporary;
|
|
} break;
|
|
|
|
case Operation::SWAP: {
|
|
uint16_t *const words = reinterpret_cast<uint16_t *>(&src.l);
|
|
const auto temporary = words[0];
|
|
words[0] = words[1];
|
|
words[1] = temporary;
|
|
|
|
status.zero_result = src.l;
|
|
status.negative_flag = temporary & 0x8000;
|
|
status.overflow_flag = status.carry_flag = 0;
|
|
} break;
|
|
|
|
/*
|
|
Shifts and rotates.
|
|
*/
|
|
#define set_neg_zero(v, m) \
|
|
status.zero_result = Status::FlagT(v); \
|
|
status.negative_flag = status.zero_result & Status::FlagT(m);
|
|
|
|
#define set_neg_zero_overflow(v, m) \
|
|
set_neg_zero(v, m); \
|
|
status.overflow_flag = (Status::FlagT(value) ^ status.zero_result) & Status::FlagT(m);
|
|
|
|
#define decode_shift_count() \
|
|
int shift_count = src.l & 63; \
|
|
flow_controller.did_shift(shift_count);
|
|
|
|
#define set_flags_w(t) set_flags(src.w, 0x8000, t)
|
|
|
|
#define asl(destination, size) {\
|
|
decode_shift_count(); \
|
|
const auto value = destination; \
|
|
\
|
|
if(!shift_count) { \
|
|
status.carry_flag = status.overflow_flag = 0; \
|
|
} else { \
|
|
destination = (shift_count < size) ? decltype(destination)(value << shift_count) : 0; \
|
|
status.extend_flag = status.carry_flag = Status::FlagT(value) & Status::FlagT( (1u << (size - 1)) >> (shift_count - 1) ); \
|
|
\
|
|
if(shift_count >= size) status.overflow_flag = value && (value != decltype(value)(-1)); \
|
|
else { \
|
|
const auto mask = decltype(destination)(0xffffffff << (size - shift_count)); \
|
|
status.overflow_flag = mask & value && ((mask & value) != mask); \
|
|
} \
|
|
} \
|
|
\
|
|
set_neg_zero(destination, 1 << (size - 1)); \
|
|
}
|
|
|
|
case Operation::ASLm: {
|
|
const auto value = src.w;
|
|
src.w = uint16_t(value << 1);
|
|
status.extend_flag = status.carry_flag = value & 0x8000;
|
|
set_neg_zero_overflow(src.w, 0x8000);
|
|
} break;
|
|
case Operation::ASLb: asl(dest.b, 8); break;
|
|
case Operation::ASLw: asl(dest.w, 16); break;
|
|
case Operation::ASLl: asl(dest.l, 32); break;
|
|
|
|
#define asr(destination, size) {\
|
|
decode_shift_count(); \
|
|
const auto value = destination; \
|
|
\
|
|
if(!shift_count) { \
|
|
status.carry_flag = 0; \
|
|
} else { \
|
|
destination = (shift_count < size) ? \
|
|
decltype(destination)(\
|
|
(value >> shift_count) | \
|
|
((value & decltype(value)(1 << (size - 1)) ? 0xffffffff : 0x000000000) << (size - shift_count)) \
|
|
) : \
|
|
decltype(destination)( \
|
|
(value & decltype(value)(1 << (size - 1))) ? 0xffffffff : 0x000000000 \
|
|
); \
|
|
status.extend_flag = status.carry_flag = Status::FlagT(value) & Status::FlagT(1 << (shift_count - 1)); \
|
|
} \
|
|
\
|
|
set_neg_zero_overflow(destination, 1 << (size - 1)); \
|
|
}
|
|
|
|
case Operation::ASRm: {
|
|
const auto value = src.w;
|
|
src.w = (value&0x8000) | (value >> 1);
|
|
status.extend_flag = status.carry_flag = value & 1;
|
|
set_neg_zero_overflow(src.w, 0x8000);
|
|
} break;
|
|
case Operation::ASRb: asr(dest.b, 8); break;
|
|
case Operation::ASRw: asr(dest.w, 16); break;
|
|
case Operation::ASRl: asr(dest.l, 32); break;
|
|
|
|
|
|
#undef set_neg_zero_overflow
|
|
#define set_neg_zero_overflow(v, m) \
|
|
set_neg_zero(v, m); \
|
|
status.overflow_flag = 0;
|
|
|
|
#undef set_flags
|
|
#define set_flags(v, m, t) \
|
|
status.zero_result = v; \
|
|
status.negative_flag = status.zero_result & (m); \
|
|
status.overflow_flag = 0; \
|
|
status.carry_flag = value & (t);
|
|
|
|
#define lsl(destination, size) {\
|
|
decode_shift_count(); \
|
|
const auto value = destination; \
|
|
\
|
|
if(!shift_count) { \
|
|
status.carry_flag = 0; \
|
|
} else { \
|
|
destination = (shift_count < size) ? decltype(destination)(value << shift_count) : 0; \
|
|
status.extend_flag = status.carry_flag = Status::FlagT(value) & Status::FlagT( (1u << (size - 1)) >> (shift_count - 1) ); \
|
|
} \
|
|
\
|
|
set_neg_zero_overflow(destination, 1 << (size - 1)); \
|
|
}
|
|
|
|
case Operation::LSLm: {
|
|
const auto value = src.w;
|
|
src.w = uint16_t(value << 1);
|
|
status.extend_flag = status.carry_flag = value & 0x8000;
|
|
set_neg_zero_overflow(src.w, 0x8000);
|
|
} break;
|
|
case Operation::LSLb: lsl(dest.b, 8); break;
|
|
case Operation::LSLw: lsl(dest.w, 16); break;
|
|
case Operation::LSLl: lsl(dest.l, 32); break;
|
|
|
|
#define lsr(destination, size) {\
|
|
decode_shift_count(); \
|
|
const auto value = destination; \
|
|
\
|
|
if(!shift_count) { \
|
|
status.carry_flag = 0; \
|
|
} else { \
|
|
destination = (shift_count < size) ? (value >> shift_count) : 0; \
|
|
status.extend_flag = status.carry_flag = value & Status::FlagT(1 << (shift_count - 1)); \
|
|
} \
|
|
\
|
|
set_neg_zero_overflow(destination, 1 << (size - 1)); \
|
|
}
|
|
|
|
case Operation::LSRm: {
|
|
const auto value = src.w;
|
|
src.w = value >> 1;
|
|
status.extend_flag = status.carry_flag = value & 1;
|
|
set_neg_zero_overflow(src.w, 0x8000);
|
|
} break;
|
|
case Operation::LSRb: lsr(dest.b, 8); break;
|
|
case Operation::LSRw: lsr(dest.w, 16); break;
|
|
case Operation::LSRl: lsr(dest.l, 32); break;
|
|
|
|
#define rol(destination, size) { \
|
|
decode_shift_count(); \
|
|
const auto value = destination; \
|
|
\
|
|
if(!shift_count) { \
|
|
status.carry_flag = 0; \
|
|
} else { \
|
|
shift_count &= (size - 1); \
|
|
destination = decltype(destination)( \
|
|
(value << shift_count) | \
|
|
(value >> (size - shift_count)) \
|
|
); \
|
|
status.carry_flag = Status::FlagT(destination & 1); \
|
|
} \
|
|
\
|
|
set_neg_zero_overflow(destination, 1 << (size - 1)); \
|
|
}
|
|
|
|
case Operation::ROLm: {
|
|
const auto value = src.w;
|
|
src.w = uint16_t((value << 1) | (value >> 15));
|
|
status.carry_flag = src.w & 1;
|
|
set_neg_zero_overflow(src.w, 0x8000);
|
|
} break;
|
|
case Operation::ROLb: rol(dest.b, 8); break;
|
|
case Operation::ROLw: rol(dest.w, 16); break;
|
|
case Operation::ROLl: rol(dest.l, 32); break;
|
|
|
|
#define ror(destination, size) { \
|
|
decode_shift_count(); \
|
|
const auto value = destination; \
|
|
\
|
|
if(!shift_count) { \
|
|
status.carry_flag = 0; \
|
|
} else { \
|
|
shift_count &= (size - 1); \
|
|
destination = decltype(destination)(\
|
|
(value >> shift_count) | \
|
|
(value << (size - shift_count)) \
|
|
);\
|
|
status.carry_flag = destination & Status::FlagT(1 << (size - 1)); \
|
|
} \
|
|
\
|
|
set_neg_zero_overflow(destination, 1 << (size - 1)); \
|
|
}
|
|
|
|
case Operation::RORm: {
|
|
const auto value = src.w;
|
|
src.w = uint16_t((value >> 1) | (value << 15));
|
|
status.carry_flag = src.w & 0x8000;
|
|
set_neg_zero_overflow(src.w, 0x8000);
|
|
} break;
|
|
case Operation::RORb: ror(dest.b, 8); break;
|
|
case Operation::RORw: ror(dest.w, 16); break;
|
|
case Operation::RORl: ror(dest.l, 32); break;
|
|
|
|
#define roxl(destination, size) { \
|
|
decode_shift_count(); \
|
|
\
|
|
shift_count %= (size + 1); \
|
|
uint64_t compound = uint64_t(destination) | (status.extend_flag ? (1ull << size) : 0); \
|
|
compound = \
|
|
(compound << shift_count) | \
|
|
(compound >> (size + 1 - shift_count)); \
|
|
status.carry_flag = status.extend_flag = Status::FlagT((compound >> size) & 1); \
|
|
destination = decltype(destination)(compound); \
|
|
\
|
|
set_neg_zero_overflow(destination, 1 << (size - 1)); \
|
|
}
|
|
|
|
case Operation::ROXLm: {
|
|
const auto value = src.w;
|
|
src.w = uint16_t((value << 1) | (status.extend_flag ? 0x0001 : 0x0000));
|
|
status.extend_flag = value & 0x8000;
|
|
set_flags_w(0x8000);
|
|
} break;
|
|
case Operation::ROXLb: roxl(dest.b, 8); break;
|
|
case Operation::ROXLw: roxl(dest.w, 16); break;
|
|
case Operation::ROXLl: roxl(dest.l, 32); break;
|
|
|
|
#define roxr(destination, size) { \
|
|
decode_shift_count(); \
|
|
\
|
|
shift_count %= (size + 1); \
|
|
uint64_t compound = uint64_t(destination) | (status.extend_flag ? (1ull << size) : 0); \
|
|
compound = \
|
|
(compound >> shift_count) | \
|
|
(compound << (size + 1 - shift_count)); \
|
|
status.carry_flag = status.extend_flag = Status::FlagT((compound >> size) & 1); \
|
|
destination = decltype(destination)(compound); \
|
|
\
|
|
set_neg_zero_overflow(destination, 1 << (size - 1)); \
|
|
}
|
|
|
|
case Operation::ROXRm: {
|
|
const auto value = src.w;
|
|
src.w = (value >> 1) | (status.extend_flag ? 0x8000 : 0x0000);
|
|
status.extend_flag = value & 0x0001;
|
|
set_flags_w(0x0001);
|
|
} break;
|
|
case Operation::ROXRb: roxr(dest.b, 8); break;
|
|
case Operation::ROXRw: roxr(dest.w, 16); break;
|
|
case Operation::ROXRl: roxr(dest.l, 32); break;
|
|
|
|
#undef roxr
|
|
#undef roxl
|
|
#undef ror
|
|
#undef rol
|
|
#undef asr
|
|
#undef lsr
|
|
#undef lsl
|
|
#undef asl
|
|
|
|
#undef set_flags
|
|
#undef decode_shift_count
|
|
#undef set_flags_w
|
|
#undef set_neg_zero_overflow
|
|
#undef set_neg_zero
|
|
|
|
case Operation::MOVEPl:
|
|
flow_controller.template movep<uint32_t>(instruction, src.l, dest.l);
|
|
break;
|
|
|
|
case Operation::MOVEPw:
|
|
flow_controller.template movep<uint16_t>(instruction, src.l, dest.l);
|
|
break;
|
|
|
|
case Operation::MOVEMtoRl:
|
|
flow_controller.template movem_toR<uint32_t>(instruction, src.l, dest.l);
|
|
break;
|
|
|
|
case Operation::MOVEMtoMl:
|
|
flow_controller.template movem_toM<uint32_t>(instruction, src.l, dest.l);
|
|
break;
|
|
|
|
case Operation::MOVEMtoRw:
|
|
flow_controller.template movem_toR<uint16_t>(instruction, src.l, dest.l);
|
|
break;
|
|
|
|
case Operation::MOVEMtoMw:
|
|
flow_controller.template movem_toM<uint16_t>(instruction, src.l, dest.l);
|
|
break;
|
|
|
|
/*
|
|
RTE and RTR share an implementation.
|
|
*/
|
|
case Operation::RTR:
|
|
flow_controller.rtr();
|
|
break;
|
|
|
|
case Operation::RTE:
|
|
flow_controller.rte();
|
|
break;
|
|
|
|
case Operation::RTS:
|
|
flow_controller.rts();
|
|
break;
|
|
|
|
/*
|
|
TSTs: compare to zero.
|
|
*/
|
|
|
|
case Operation::TSTb:
|
|
status.carry_flag = status.overflow_flag = 0;
|
|
status.zero_result = src.b;
|
|
status.negative_flag = status.zero_result & 0x80;
|
|
break;
|
|
|
|
case Operation::TSTw:
|
|
status.carry_flag = status.overflow_flag = 0;
|
|
status.zero_result = src.w;
|
|
status.negative_flag = status.zero_result & 0x8000;
|
|
break;
|
|
|
|
case Operation::TSTl:
|
|
status.carry_flag = status.overflow_flag = 0;
|
|
status.zero_result = src.l;
|
|
status.negative_flag = status.zero_result & 0x80000000;
|
|
break;
|
|
|
|
case Operation::STOP:
|
|
status.set_status(src.w);
|
|
flow_controller.did_update_status();
|
|
flow_controller.stop();
|
|
break;
|
|
|
|
case Operation::RESET:
|
|
flow_controller.reset();
|
|
break;
|
|
|
|
/*
|
|
Development period debugging.
|
|
*/
|
|
default:
|
|
assert(false);
|
|
break;
|
|
}
|
|
#undef sub_overflow
|
|
#undef add_overflow
|
|
|
|
#undef u_extend16
|
|
#undef s_extend16
|
|
|
|
}
|
|
|
|
}
|
|
}
|
|
|
|
#endif /* InstructionSets_M68k_PerformImplementation_h */
|