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77 lines
2.0 KiB
C++
77 lines
2.0 KiB
C++
//
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// DiskROM.cpp
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// Clock Signal
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//
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// Created by Thomas Harte on 07/01/2018.
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// Copyright 2018 Thomas Harte. All rights reserved.
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//
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#include "DiskROM.hpp"
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using namespace MSX;
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DiskROM::DiskROM(const std::vector<uint8_t> &rom) :
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WD1770(P1793),
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rom_(rom) {
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drives_[0] = std::make_shared<Storage::Disk::Drive>(8000000, 300, 2);
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drives_[1] = std::make_shared<Storage::Disk::Drive>(8000000, 300, 2);
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set_is_double_density(true);
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}
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void DiskROM::write(uint16_t address, uint8_t value, bool pc_is_outside_bios) {
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switch(address) {
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case 0x7ff8: case 0x7ff9: case 0x7ffa: case 0x7ffb:
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WD::WD1770::write(address, value);
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break;
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case 0x7ffc:
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selected_head_ = value & 1;
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drives_[0]->set_head(selected_head_);
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drives_[1]->set_head(selected_head_);
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break;
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case 0x7ffd: {
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selected_drive_ = value & 1;
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set_drive(drives_[selected_drive_]);
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bool drive_motor = !!(value & 0x80);
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drives_[0]->set_motor_on(drive_motor);
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drives_[1]->set_motor_on(drive_motor);
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} break;
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}
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}
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uint8_t DiskROM::read(uint16_t address) {
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if(address >= 0x7ff8 && address < 0x7ffc) {
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return WD::WD1770::read(address);
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}
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if(address == 0x7fff) {
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return (get_data_request_line() ? 0x00 : 0x80) | (get_interrupt_request_line() ? 0x00 : 0x40);
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}
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return rom_[address & 0x3fff];
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}
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void DiskROM::run_for(HalfCycles half_cycles) {
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// Input clock is going to be 7159090/2 Mhz, but the drive controller
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// needs an 8Mhz clock, so scale up. 8000000/7159090 simplifies to
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// 800000/715909.
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controller_cycles_ += 800000 * half_cycles.as_integral();
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WD::WD1770::run_for(Cycles(static_cast<int>(controller_cycles_ / 715909)));
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controller_cycles_ %= 715909;
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}
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void DiskROM::set_disk(std::shared_ptr<Storage::Disk::Disk> disk, size_t drive) {
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drives_[drive]->set_disk(disk);
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}
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void DiskROM::set_head_load_request(bool head_load) {
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// Magic!
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set_head_loaded(head_load);
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}
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void DiskROM::set_activity_observer(Activity::Observer *observer) {
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size_t c = 1;
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for(auto &drive: drives_) {
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drive->set_activity_observer(observer, "Drive " + std::to_string(c), true);
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++c;
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}
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}
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