mirror of
https://github.com/TomHarte/CLK.git
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154 lines
2.8 KiB
XML
154 lines
2.8 KiB
XML
;
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; Fichier de script CSL
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; Execution du module SHAKE26C du DSK SHAKER26.DSK en CRTC 2
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; Le module genere des instructions au format SSM
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;
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csl_version 1.0
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crtc_select 2
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reset
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wait 3000000
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disk_insert 'shaker26.dsk'
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key_delay 70000 70000 400000
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key_output 'RUN"SHAKE26C"\(RET)'
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wait 10000000
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;
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; test 5 Parity Check Select CRTC 0, 2
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key_output '5'
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wait 10000000
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key_output ' '
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wait 1000000 ; menu
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; C9 IVM Switch
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key_output '6'
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wait 1200000 ; 29f
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key_output ' '
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wait 1200000 ; 2a4
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key_output ' '
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wait 1200000 ; 2a5
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key_output ' '
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wait 1200000 ; 2a6
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key_output ' '
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wait 1200000 ; 2a7
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key_output ' '
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wait 1200000 ; 2ac
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key_output ' '
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wait 1200000 ; 2ad
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key_output ' '
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wait 1200000 ; 2ae
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key_output ' '
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wait 1200000 ; 2af
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key_output ' '
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wait 1200000 ; 2b4
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key_output ' '
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wait 1200000 ; 2b5
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key_output ' '
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wait 1200000 ; 2b6
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key_output ' '
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wait 1200000 ; 2b7
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key_output ' '
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wait 1200000 ; 2bc
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key_output ' '
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wait 1200000 ; 2bd
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key_output ' '
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wait 1200000 ; 2be
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key_output ' '
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wait 1000000 ; menu
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; test prevu pour CRTC 2 mais disp autre crc Last Line cond
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key_output '7'
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wait 64000000
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key_output ' '
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wait 1000000 ; menu
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;
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; add line on parity bug
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key_output '8'
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wait 2000000 ; 2c0
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key_output ' '
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wait 2000000 ; 2c1
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key_output ' '
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wait 2000000 ; 2c2
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key_output ' '
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wait 2000000 ; 2c3
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key_output ' '
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wait 2000000 ; 2c4
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key_output ' '
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wait 2000000 ; 2c5
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key_output ' '
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wait 2000000 ; 2c6
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key_output ' '
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wait 1000000 ; menu
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; add line rq & trigger
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key_output '9'
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wait 2000000 ; 2c7
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key_output ' '
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wait 300000000
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key_output ' '
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; test crtc 2 vma' sur R1=0
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key_output 'T'
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wait 1100000
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key_output ' '
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wait 1200000
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key_output ' '
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wait 1200000
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key_output ' '
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wait 1200000
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key_output ' '
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wait 1000000 ; menu
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; crtc 2 ghost vsync vs Last Line (others crtc welcome)
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key_output '\(RET)'
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wait 5000000
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key_output ' '
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wait 2000000
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key_output ' '
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wait 1000000 ; menu
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; Add Line R5 on last line
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key_output 'E'
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wait 20000000
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key_output ' '
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wait 10000000
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key_output ' '
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wait 1000000 ; menu
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; Add line R8
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key_output 'P'
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wait 20000000
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key_output ' '
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wait 1000000 ; menu
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; r5 additional line in interlace mode
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key_output 'S'
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wait 2000000
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key_output ' '
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wait 1000000 ; menu
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; CRTC 2 Interlace vsync nightmare (2 1er test uniqu CRTC1)
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key_output 'O'
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wait 6000000 ; cvstot
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key_output ' '
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wait 2000000 ; parity00 2d8
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wait 8000000 ; 2d9
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key_output ' '
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wait 10000000 ; cvms_a ; 2da
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key_output ' '
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wait 10000000 ; cvms_b ; 2db
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key_output ' '
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wait 10000000 ; cvms_b ; 2dc
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key_output ' '
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wait 10000000 ; cvms_c ; 2dd
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key_output ' '
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wait 10000000 ; cvms_c ; 2de
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key_output ' '
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wait 10000000 ; menu
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; R9/R4 UPD LAST LIMIT
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key_output 'R'
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wait 5000000 ; 3ad
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key_output ' '
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wait 10000000 ; menu
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csl_load 'SHAKE26C-4' ; corrected from cls_load |