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154 lines
2.7 KiB
C++
154 lines
2.7 KiB
C++
//
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// x86.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 1/1/21.
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// Copyright © 2021 Thomas Harte. All rights reserved.
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//
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#ifndef x86_hpp
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#define x86_hpp
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#include <cstddef>
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#include <cstdint>
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namespace CPU {
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namespace Decoder {
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namespace x86 {
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enum class Model {
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i8086,
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};
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enum class Operation: uint8_t {
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Invalid,
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AAA, AAD, AAM, AAS, ADC, ADD, AND, CALL, CBW, CLC, CLD, CLI, CMC,
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CMP, CMPS, CWD, DAA, DAS, DEC, DIV, ESC, HLT, IDIV, IMUL, IN,
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INC, INT, INTO, IRET,
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JO, JNO,
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JB, JNB,
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JE, JNE,
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JBE, JNBE,
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JS, JNS,
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JP, JNP,
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JL, JNL,
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JLE, JNLE,
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JMP, JCXZ,
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LAHF, LDS, LEA,
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LODS, LOOPE, LOOPNE, MOV, MOVS, MUL, NEG, NOP, NOT, OR, OUT,
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POP, POPF, PUSH, PUSHF, RCL, RCR, REP, RET, ROL, ROR, SAHF,
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SAR, SBB, SCAS, SHL, SHR, STC, STD, STI, STOS, SUB, TEST,
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WAIT, XCHG, XLAT, XOR
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};
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enum class Size: uint8_t {
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Implied = 0,
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Byte = 1,
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Word = 2,
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DWord = 4,
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};
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enum class Source: uint8_t {
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None,
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AL, AH, AX,
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BL, BH, BX,
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CL, CH, CX,
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DL, DH, DX,
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CS, DS, ES, SS,
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SI, DI,
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BP, SP,
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IndBXPlusSI,
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IndBXPlusDI,
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IndBPPlusSI,
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IndBPPlusDI,
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IndSI,
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IndDI,
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DirectAddress,
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IndBP,
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IndBX,
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Immediate
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};
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class Instruction {
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public:
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const Operation operation = Operation::Invalid;
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const Size operand_size = Size::Byte;
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const Source source = Source::AL;
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const Source destination = Source::AL;
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int size() const {
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return size_;
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}
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private:
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int size_ = 0;
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};
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/*!
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Implements Intel x86 instruction decoding.
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This is an experimental implementation; it has not yet undergone significant testing.
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*/
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struct Decoder {
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public:
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Decoder(Model model);
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/*!
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@returns an @c Instruction with a positive size to indicate successful decoding; a
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negative size specifies the number of further bytes required fully to decode, and
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a zero size indicates that further bytes are required but the decoder does not yet
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know exactly how many.
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*/
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Instruction decode(uint8_t *source, size_t length);
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private:
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enum class Phase {
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Instruction,
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ModRM,
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AwaitingOperands,
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ReadyToPost
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} phase_ = Phase::Instruction;
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enum class Format: uint8_t {
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MemReg_Reg,
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Reg_MemReg,
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Ac_Data,
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MemReg_Data,
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SegReg_MemReg,
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Reg_Addr,
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Addr_Reg,
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Disp,
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Addr
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} format_ = Format::MemReg_Reg;
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// TODO: figure out which Formats can be folded together,
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// and which are improperly elided.
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enum class Repetition: uint8_t {
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None, RepE, RepNE
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} repetition_ = Repetition::None;
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int consumed_ = 0;
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Operation operation_ = Operation::Invalid;
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bool large_operand_ = false;
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Source source_ = Source::None;
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Source destination_ = Source::None;
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Source segment_override_ = Source::None;
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uint8_t instr_ = 0x00;
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bool lock_ = false;
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bool add_offset_ = false;
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bool large_offset_ = false;
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};
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}
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}
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}
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#endif /* x86_hpp */
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