1
0
mirror of https://github.com/TomHarte/CLK.git synced 2024-11-26 23:52:26 +00:00
CLK/Components
2023-01-17 21:18:56 -05:00
..
1770 WD1770: switch motor on even if spin-up is disabled. 2021-06-21 23:26:55 -04:00
5380 Continue DMA requests if writing, even after a phase mismatch. 2022-09-15 16:46:22 -04:00
6522 Eliminate unused #includes. 2021-07-18 11:35:57 -04:00
6526 Avoid unnecessary get_port_input calls. 2021-11-24 17:15:48 -05:00
6532 Starts to add Qt target; resolves many build warnings. 2020-05-30 00:37:06 -04:00
6560 Switch name back to emphasise _async_. 2022-07-16 14:41:04 -04:00
6845 Further doubles down on construction syntax for type conversions. 2020-05-09 23:00:39 -04:00
6850 Introduce the principle that a Serial::Line can be two-wire — clock + data. 2021-11-06 16:54:20 -07:00
8255 Starts to add Qt target; resolves many build warnings. 2020-05-30 00:37:06 -04:00
8272 Adds a Qt timer class. Precision seems to be 'acceptable'. 2020-05-31 23:39:08 -04:00
8530 Ensures no double definition of NDEBUG. 2021-03-07 12:52:54 -05:00
9918 Eliminate hard-coded assumption of 16kb. 2023-01-10 12:38:19 -05:00
68901 Fix include order. 2023-01-14 14:16:56 -05:00
AppleClock Establishes valid initial BRAM. 2021-09-10 19:56:20 -04:00
AudioToggle Switch name back to emphasise _async_. 2022-07-16 14:41:04 -04:00
AY38910 Switch name back to emphasise _async_. 2022-07-16 14:41:04 -04:00
DiskII Walk back slightly. 2021-10-14 18:02:58 -07:00
KonamiSCC Switch name back to emphasise _async_. 2022-07-16 14:41:04 -04:00
OPx Switch name back to emphasise _async_. 2022-07-16 14:41:04 -04:00
RP5C01 Make read consistent. 2023-01-17 21:18:56 -05:00
Serial Add header for assert. 2021-11-24 16:28:18 -05:00
SN76489 Switch name back to emphasise _async_. 2022-07-16 14:41:04 -04:00