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116 lines
3.4 KiB
C++
116 lines
3.4 KiB
C++
//
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// 68000Storage.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 08/03/2019.
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// Copyright © 2019 Thomas Harte. All rights reserved.
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//
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#ifndef MC68000Storage_h
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#define MC68000Storage_h
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class ProcessorStorage {
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public:
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ProcessorStorage();
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protected:
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RegisterPair32 data_[8];
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RegisterPair32 address_[7];
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RegisterPair32 stack_pointers_[2]; // [0] = user stack pointer; [1] = supervisor
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RegisterPair32 program_counter_;
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RegisterPair16 prefetch_queue_[2];
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bool dtack_ = true;
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// Various status bits.
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int is_supervisor_;
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// Generic sources and targets for memory operations.
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uint32_t effective_address_;
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RegisterPair32 bus_data_;
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/*!
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A step is a microcycle to perform plus an action to occur afterwards, if any.
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*/
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struct Step {
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Microcycle microcycle;
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enum class Action {
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None,
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/// Performs effective_address_ += 2.
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IncrementEffectiveAddress,
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/// Performs program_counter_ += 2.
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IncrementProgramCounter,
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/// Copies prefetch_queue_[1] to prefetch_queue_[0].
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AdvancePrefetch,
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/*!
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Terminates an atomic program; if nothing else is pending, schedules the next instruction.
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This action is special in that it usurps any included microcycle. So any Step with this
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as its action acts as an end-of-list sentinel.
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*/
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ScheduleNextProgram
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} action = Action::None;
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};
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// Special programs.
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std::vector<Step> reset_program_;
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// Current program pointer.
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Step *active_program_ = nullptr;
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private:
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/*!
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Produces a vector of Steps that implement the described program.
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@param access_pattern A string describing the bus activity that occurs
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during this program. This should follow the same general pattern as
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those in yacht.txt; full description below.
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@discussion
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The access pattern is defined, as in yacht.txt, to be a string consisting
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of the following discrete bus actions. Spaces are ignored.
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* n: no operation; data bus is not used;
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* -: idle state; data bus is not used but is also not available;
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* p: program fetch; reads from the PC and adds two to it;
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* W: write MSW of something onto the bus;
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* w: write LSW of something onto the bus;
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* R: read MSW of something from the bus;
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* r: read LSW of soemthing from the bus;
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* S: push the MSW of something onto the stack;
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* s: push the LSW of something onto the stack;
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* U: pop the MSW of something from the stack;
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* u: pop the LSW of something from the stack;
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* V: fetch a vector's MSW;
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* v: fetch a vector's LSW;
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* i: acquire interrupt vector in an IACK cycle;
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* F: fetch the SSPs MSW;
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* f: fetch the SSP's LSW.
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Quite a lot of that is duplicative, implying both something about internal
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state and something about what's observable on the bus, but it's helpful to
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stick to that document's coding exactly for easier debugging.
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p fetches will fill the prefetch queue, attaching an action to both the
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step that precedes them and to themselves. The SSP fetches will go straight
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to the SSP.
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Other actions will by default act via effective_address_ and bus_data_.
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The user should fill in the steps necessary to get data into or extract
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data from those.
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*/
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std::vector<Step> assemble_program(const char *access_pattern);
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/*!
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Disassembles the instruction @c instruction and inserts it into the
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appropriate lookup tables.
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*/
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void install_instruction(int instruction);
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};
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#endif /* MC68000Storage_h */
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