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554 lines
17 KiB
C++
554 lines
17 KiB
C++
//
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// OperationMapper.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 16/02/2024.
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// Copyright © 2024 Thomas Harte. All rights reserved.
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//
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#pragma once
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#include "../../Reflection/Dispatcher.hpp"
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#include "BarrelShifter.hpp"
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namespace InstructionSet::ARM {
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enum class Model {
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ARMv2,
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/// Like an ARMv2 but all non-PC addressing is 64-bit. Primarily useful for a particular set of test
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/// cases that I want to apply retroactively; not a real iteration.
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ARMv2with32bitAddressing,
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};
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enum class Condition {
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EQ, NE, CS, CC,
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MI, PL, VS, VC,
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HI, LS, GE, LT,
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GT, LE, AL, NV,
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};
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//
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// Implementation details.
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//
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static constexpr int FlagsStartBit = 20;
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using Flags = uint8_t;
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template <int position>
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constexpr bool flag_bit(const uint8_t flags) {
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static_assert(position >= 20 && position < 28);
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return flags & (1 << (position - FlagsStartBit));
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}
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//
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// Methods common to data processing and data transfer.
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//
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struct WithShiftControlBits {
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constexpr WithShiftControlBits(const uint32_t opcode) noexcept : opcode_(opcode) {}
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/// The operand 2 register index if @c operand2_is_immediate() is @c false; meaningless otherwise.
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uint32_t operand2() const { return opcode_ & 0xf; }
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/// The type of shift to apply to operand 2 if @c operand2_is_immediate() is @c false; meaningless otherwise.
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ShiftType shift_type() const { return ShiftType((opcode_ >> 5) & 3); }
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/// @returns @c true if the amount to shift by should be taken from a register; @c false if it is an immediate value.
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bool shift_count_is_register() const { return opcode_ & (1 << 4); }
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/// The shift amount register index if @c shift_count_is_register() is @c true; meaningless otherwise.
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uint32_t shift_register() const { return (opcode_ >> 8) & 0xf; }
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/// The amount to shift by if @c shift_count_is_register() is @c false; meaningless otherwise.
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uint32_t shift_amount() const { return (opcode_ >> 7) & 0x1f; }
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protected:
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uint32_t opcode_;
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};
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//
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// Branch (i.e. B and BL).
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//
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struct BranchFlags {
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constexpr BranchFlags(const uint8_t flags) noexcept : flags_(flags) {}
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enum class Operation {
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B, /// Add offset to PC; programmer allows for PC being two words ahead.
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BL, /// Copy PC and PSR to R14, then branch. Copied PC points to next instruction.
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};
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/// @returns The operation to apply.
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constexpr Operation operation() const {
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return flag_bit<24>(flags_) ? Operation::BL : Operation::B;
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}
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private:
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uint8_t flags_;
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};
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struct Branch {
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constexpr Branch(const uint32_t opcode) noexcept : opcode_(opcode) {}
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/// The 26-bit offset to add to the PC.
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uint32_t offset() const { return (opcode_ & 0xff'ffff) << 2; }
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private:
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uint32_t opcode_;
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};
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//
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// Data processing (i.e. AND to MVN).
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//
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enum class DataProcessingOperation {
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AND, /// Rd = Op1 AND Op2.
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EOR, /// Rd = Op1 EOR Op2.
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SUB, /// Rd = Op1 - Op2.
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RSB, /// Rd = Op2 - Op1.
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ADD, /// Rd = Op1 + Op2.
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ADC, /// Rd = Op1 + Ord2 + C.
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SBC, /// Rd = Op1 - Op2 + C.
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RSC, /// Rd = Op2 - Op1 + C.
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TST, /// Set condition codes on Op1 AND Op2.
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TEQ, /// Set condition codes on Op1 EOR Op2.
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CMP, /// Set condition codes on Op1 - Op2.
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CMN, /// Set condition codes on Op1 + Op2.
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ORR, /// Rd = Op1 OR Op2.
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MOV, /// Rd = Op2
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BIC, /// Rd = Op1 AND NOT Op2.
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MVN, /// Rd = NOT Op2.
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};
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constexpr bool is_logical(const DataProcessingOperation operation) {
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switch(operation) {
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case DataProcessingOperation::AND:
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case DataProcessingOperation::EOR:
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case DataProcessingOperation::TST:
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case DataProcessingOperation::TEQ:
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case DataProcessingOperation::ORR:
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case DataProcessingOperation::MOV:
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case DataProcessingOperation::BIC:
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case DataProcessingOperation::MVN:
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return true;
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default: return false;
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}
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}
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constexpr bool is_comparison(const DataProcessingOperation operation) {
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switch(operation) {
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case DataProcessingOperation::TST:
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case DataProcessingOperation::TEQ:
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case DataProcessingOperation::CMP:
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case DataProcessingOperation::CMN:
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return true;
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default: return false;
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}
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}
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struct DataProcessingFlags {
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constexpr DataProcessingFlags(const uint8_t flags) noexcept : flags_(flags) {}
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/// @returns The operation to apply.
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constexpr DataProcessingOperation operation() const {
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return DataProcessingOperation((flags_ >> (21 - FlagsStartBit)) & 0xf);
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}
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/// @returns @c true if operand 2 is defined by the @c rotate() and @c immediate() fields;
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/// @c false if it is defined by the @c shift_*() and @c operand2() fields.
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constexpr bool operand2_is_immediate() const { return flag_bit<25>(flags_); }
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/// @c true if the status register should be updated; @c false otherwise.
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constexpr bool set_condition_codes() const { return flag_bit<20>(flags_); }
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private:
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uint8_t flags_;
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};
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struct DataProcessing: public WithShiftControlBits {
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using WithShiftControlBits::WithShiftControlBits;
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/// The destination register index. i.e. Rd.
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uint32_t destination() const { return (opcode_ >> 12) & 0xf; }
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/// The operand 1 register index. i.e. Rn.
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uint32_t operand1() const { return (opcode_ >> 16) & 0xf; }
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//
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// Immediate values for operand 2.
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//
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/// An 8-bit value to rotate right @c rotate() places if @c operand2_is_immediate() is @c true; meaningless otherwise.
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uint32_t immediate() const { return opcode_ & 0xff; }
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/// The number of bits to rotate @c immediate() by to the right if @c operand2_is_immediate() is @c true; meaningless otherwise.
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uint32_t rotate() const { return (opcode_ >> 7) & 0x1e; }
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};
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//
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// MUL and MLA.
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//
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struct MultiplyFlags {
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constexpr MultiplyFlags(const uint8_t flags) noexcept : flags_(flags) {}
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/// @c true if the status register should be updated; @c false otherwise.
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constexpr bool set_condition_codes() const { return flag_bit<20>(flags_); }
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enum class Operation {
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MUL, /// Rd = Rm * Rs
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MLA, /// Rd = Rm * Rs + Rn
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};
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/// @returns The operation to apply.
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constexpr Operation operation() const {
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return flag_bit<21>(flags_) ? Operation::MLA : Operation::MUL;
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}
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private:
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uint8_t flags_;
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};
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struct Multiply {
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constexpr Multiply(const uint32_t opcode) noexcept : opcode_(opcode) {}
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/// The destination register index. i.e. 'Rd'.
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uint32_t destination() const { return (opcode_ >> 16) & 0xf; }
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/// The accumulator register index for multiply-add. i.e. 'Rn'.
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uint32_t accumulator() const { return (opcode_ >> 12) & 0xf; }
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/// The multiplicand register index. i.e. 'Rs'.
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uint32_t multiplicand() const { return (opcode_ >> 8) & 0xf; }
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/// The multiplier register index. i.e. 'Rm'.
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uint32_t multiplier() const { return opcode_ & 0xf; }
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private:
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uint32_t opcode_;
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};
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//
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// Single data transfer (LDR, STR).
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//
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struct SingleDataTransferFlags {
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constexpr SingleDataTransferFlags(const uint8_t flags) noexcept : flags_(flags) {}
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enum class Operation {
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LDR, /// Read single byte or word from [base + offset], possibly mutating the base.
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STR, /// Write a single byte or word to [base + offset], possibly mutating the base.
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};
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constexpr Operation operation() const {
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return flag_bit<20>(flags_) ? Operation::LDR : Operation::STR;
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}
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constexpr bool offset_is_register() const { return flag_bit<25>(flags_); }
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constexpr bool pre_index() const { return flag_bit<24>(flags_); }
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constexpr bool add_offset() const { return flag_bit<23>(flags_); }
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constexpr bool transfer_byte() const { return flag_bit<22>(flags_); }
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constexpr bool write_back_address() const { return flag_bit<21>(flags_); }
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private:
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uint8_t flags_;
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};
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struct SingleDataTransfer: public WithShiftControlBits {
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using WithShiftControlBits::WithShiftControlBits;
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/// The destination register index. i.e. 'Rd' for LDR.
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uint32_t destination() const { return (opcode_ >> 12) & 0xf; }
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/// The destination register index. i.e. 'Rd' for STR.
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uint32_t source() const { return (opcode_ >> 12) & 0xf; }
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/// The base register index. i.e. 'Rn'.
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uint32_t base() const { return (opcode_ >> 16) & 0xf; }
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/// The immediate offset, if @c offset_is_register() was @c false; meaningless otherwise.
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uint32_t immediate() const { return opcode_ & 0xfff; }
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};
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//
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// Block data transfer (LDR, STR).
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//
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struct BlockDataTransferFlags {
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constexpr BlockDataTransferFlags(const uint8_t flags) noexcept : flags_(flags) {}
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enum class Operation {
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LDM, /// Read 1–16 words from [base], possibly mutating it.
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STM, /// Write 1-16 words to [base], possibly mutating it.
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};
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constexpr Operation operation() const {
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return flag_bit<20>(flags_) ? Operation::LDM : Operation::STM;
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}
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constexpr bool pre_index() const { return flag_bit<24>(flags_); }
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constexpr bool add_offset() const { return flag_bit<23>(flags_); }
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constexpr bool load_psr() const { return flag_bit<22>(flags_); }
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constexpr bool write_back_address() const { return flag_bit<21>(flags_); }
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private:
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uint8_t flags_;
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};
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struct BlockDataTransfer: public WithShiftControlBits {
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using WithShiftControlBits::WithShiftControlBits;
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/// The base register index. i.e. 'Rn'.
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uint32_t base() const { return (opcode_ >> 16) & 0xf; }
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/// A bitfield indicating which registers to load or store.
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uint16_t register_list() const { return static_cast<uint16_t>(opcode_); }
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uint32_t popcount() const {
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const uint16_t list = register_list();
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// TODO: just use std::popcount when adopting C++20.
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uint32_t total = ((list & 0xaaaa) >> 1) + (list & 0x5555);
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total = ((total & 0xcccc) >> 2) + (total & 0x3333);
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total = ((total & 0xf0f0) >> 4) + (total & 0x0f0f);
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total = ((total & 0xff00) >> 8) + (total & 0x00ff);
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return total;
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}
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};
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//
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// Coprocessor data operation.
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//
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struct CoprocessorDataOperationFlags {
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constexpr CoprocessorDataOperationFlags(const uint8_t flags) noexcept : flags_(flags) {}
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constexpr int coprocessor_operation() const { return (flags_ >> (FlagsStartBit - 20)) & 0xf; }
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private:
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uint8_t flags_;
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};
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struct CoprocessorDataOperation {
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constexpr CoprocessorDataOperation(const uint32_t opcode) noexcept : opcode_(opcode) {}
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uint32_t operand1() const { return (opcode_ >> 16) & 0xf; }
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uint32_t operand2() const { return opcode_ & 0xf; }
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uint32_t destination() const { return (opcode_ >> 12) & 0xf; }
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uint32_t coprocessor() const { return (opcode_ >> 8) & 0xf; }
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uint32_t information() const { return (opcode_ >> 5) & 0x7; }
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private:
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uint32_t opcode_;
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};
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//
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// Coprocessor register transfer.
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//
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struct CoprocessorRegisterTransferFlags {
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constexpr CoprocessorRegisterTransferFlags(const uint8_t flags) noexcept : flags_(flags) {}
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enum class Operation {
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MRC, /// Move from coprocessor register to ARM register.
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MCR, /// Move from ARM register to coprocessor register.
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};
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constexpr Operation operation() const {
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return flag_bit<20>(flags_) ? Operation::MRC : Operation::MCR;
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}
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constexpr int coprocessor_operation() const { return (flags_ >> (FlagsStartBit - 20)) & 0x7; }
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private:
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uint8_t flags_;
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};
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struct CoprocessorRegisterTransfer {
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constexpr CoprocessorRegisterTransfer(const uint32_t opcode) noexcept : opcode_(opcode) {}
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uint32_t operand1() const { return (opcode_ >> 16) & 0xf; }
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uint32_t operand2() const { return opcode_ & 0xf; }
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uint32_t destination() const { return (opcode_ >> 12) & 0xf; }
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uint32_t coprocessor() const { return (opcode_ >> 8) & 0xf; }
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uint32_t information() const { return (opcode_ >> 5) & 0x7; }
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private:
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uint32_t opcode_;
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};
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//
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// Coprocessor data transfer.
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//
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struct CoprocessorDataTransferFlags {
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constexpr CoprocessorDataTransferFlags(const uint8_t flags) noexcept : flags_(flags) {}
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enum class Operation {
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LDC, /// Coprocessor data transfer load.
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STC, /// Coprocessor data transfer store.
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};
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constexpr Operation operation() const {
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return flag_bit<20>(flags_) ? Operation::LDC : Operation::STC;
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}
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constexpr bool pre_index() const { return flag_bit<24>(flags_); }
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constexpr bool add_offset() const { return flag_bit<23>(flags_); }
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constexpr bool transfer_length() const { return flag_bit<22>(flags_); }
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constexpr bool write_back_address() const { return flag_bit<21>(flags_); }
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private:
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uint8_t flags_;
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};
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//
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// Software interrupt.
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//
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struct SoftwareInterrupt {
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constexpr SoftwareInterrupt(const uint32_t opcode) noexcept : opcode_(opcode) {}
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/// The 24-bit comment field, often decoded by the receiver of an SWI.
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uint32_t comment() const { return opcode_ & 0xff'ffff; }
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private:
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uint32_t opcode_;
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};
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struct CoprocessorDataTransfer {
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constexpr CoprocessorDataTransfer(const uint32_t opcode) noexcept : opcode_(opcode) {}
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int base() const { return (opcode_ >> 16) & 0xf; }
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int source() const { return (opcode_ >> 12) & 0xf; }
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int destination() const { return (opcode_ >> 12) & 0xf; }
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int coprocessor() const { return (opcode_ >> 8) & 0xf; }
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int offset() const { return opcode_ & 0xff; }
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private:
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uint32_t opcode_;
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};
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/// Operation mapper; use the free function @c dispatch as defined below.
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template <Model>
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struct OperationMapper {
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static Condition condition(const uint32_t instruction) {
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return Condition(instruction >> 28);
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}
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template <int i, typename SchedulerT>
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static void dispatch(const uint32_t instruction, SchedulerT &scheduler) {
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// Put the 8-bit segment of instruction back into its proper place;
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// this allows all the tests below to be written so as to coordinate
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// properly with the data sheet, and since it's all compile-time work
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// it doesn't cost anything.
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constexpr auto partial = uint32_t(i << 20);
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// Cf. the ARM2 datasheet, p.45. Tests below match its ordering
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// other than that 'undefined' is the fallthrough case. More specific
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// page references are provided were more detailed versions of the
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// decoding are depicted.
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// Multiply and multiply-accumulate (MUL, MLA); cf. p.23.
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//
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// This usurps a potential data processing decoding, so needs priority.
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if constexpr (((partial >> 22) & 0b111'111) == 0b000'000) {
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// This implementation provides only eight bits baked into the template parameters so
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// an additional dynamic test is required to check whether this is really, really MUL or MLA.
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if((instruction & 0b1111'0000) == 0b1001'0000) {
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scheduler.template perform<i>(Multiply(instruction));
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return;
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}
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}
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// Data processing; cf. p.17.
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if constexpr (((partial >> 26) & 0b11) == 0b00) {
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scheduler.template perform<i>(DataProcessing(instruction));
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return;
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}
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// Single data transfer (LDR, STR); cf. p.25.
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if constexpr (((partial >> 26) & 0b11) == 0b01) {
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scheduler.template perform<i>(SingleDataTransfer(instruction));
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return;
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}
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// Block data transfer (LDM, STM); cf. p.29.
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if constexpr (((partial >> 25) & 0b111) == 0b100) {
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scheduler.template perform<i>(BlockDataTransfer(instruction));
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return;
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}
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// Branch and branch with link (B, BL); cf. p.15.
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if constexpr (((partial >> 25) & 0b111) == 0b101) {
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scheduler.template perform<i>(Branch(instruction));
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return;
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}
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// Software interreupt; cf. p.35.
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if constexpr (((partial >> 24) & 0b1111) == 0b1111) {
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scheduler.software_interrupt(SoftwareInterrupt(instruction));
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return;
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}
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// Both:
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// Coprocessor data operation; cf. p. 37; and
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// Coprocessor register transfers; cf. p. 42.
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if constexpr (((partial >> 24) & 0b1111) == 0b1110) {
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if(instruction & (1 << 4)) {
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// Register transfer.
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scheduler.template perform<i>(CoprocessorRegisterTransfer(instruction));
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} else {
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// Data operation.
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scheduler.template perform<i>(CoprocessorDataOperation(instruction));
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}
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return;
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}
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// Coprocessor data transfers; cf. p.39.
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if constexpr (((partial >> 25) & 0b111) == 0b110) {
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scheduler.template perform<i>(CoprocessorDataTransfer(instruction));
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return;
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}
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// Fallback position.
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scheduler.unknown();
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||
}
|
||
};
|
||
|
||
/// A brief documentation of the interface expected by @c dispatch below; will be a concept if/when this project adopts C++20.
|
||
struct SampleScheduler {
|
||
/// @returns @c true if the rest of the instruction should be decoded and supplied
|
||
/// to the scheduler as defined below; @c false otherwise.
|
||
bool should_schedule(Condition);
|
||
|
||
// Template argument:
|
||
//
|
||
// Flags, an opaque type which can be converted into a DataProcessingFlags, MultiplyFlags, etc,
|
||
// by simple construction, to provide all flags that can be baked into the template parameters.
|
||
//
|
||
// Function argument:
|
||
//
|
||
// An operation-specific encapsulation of the operation code for decoding of fields that didn't
|
||
// fit into the template parameters.
|
||
//
|
||
// Either or both may be omitted if unnecessary.
|
||
template <Flags> void perform(DataProcessing);
|
||
template <Flags> void perform(Multiply);
|
||
template <Flags> void perform(SingleDataTransfer);
|
||
template <Flags> void perform(BlockDataTransfer);
|
||
template <Flags> void perform(Branch);
|
||
template <Flags> void perform(CoprocessorRegisterTransfer);
|
||
template <Flags> void perform(CoprocessorDataOperation);
|
||
template <Flags> void perform(CoprocessorDataTransfer);
|
||
|
||
// Irregular operations.
|
||
void software_interrupt(SoftwareInterrupt);
|
||
void unknown();
|
||
};
|
||
|
||
/// Decodes @c instruction, making an appropriate call into @c scheduler.
|
||
///
|
||
/// In lieu of C++20, see the sample definition of SampleScheduler above for the expected interface.
|
||
template <Model model, typename SchedulerT> void dispatch(const uint32_t instruction, SchedulerT &scheduler) {
|
||
OperationMapper<model> mapper;
|
||
|
||
// Test condition.
|
||
const auto condition = mapper.condition(instruction);
|
||
if(!scheduler.should_schedule(condition)) {
|
||
return;
|
||
}
|
||
|
||
// Dispatch body.
|
||
Reflection::dispatch(mapper, (instruction >> FlagsStartBit) & 0xff, instruction, scheduler);
|
||
}
|
||
|
||
}
|