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544 lines
14 KiB
C++
544 lines
14 KiB
C++
//
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// Z80.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 14/05/2017.
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// Copyright 2017 Thomas Harte. All rights reserved.
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//
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#ifndef Z80_hpp
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#define Z80_hpp
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#include <cassert>
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#include <vector>
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#include <cstdint>
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#include "../RegisterSizes.hpp"
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#include "../../ClockReceiver/ClockReceiver.hpp"
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#include "../../ClockReceiver/ForceInline.hpp"
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namespace CPU {
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namespace Z80 {
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/*
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The list of registers that can be accessed via @c set_value_of_register and @c set_value_of_register.
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*/
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enum class Register {
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ProgramCounter,
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StackPointer,
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A, Flags, AF,
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B, C, BC,
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D, E, DE,
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H, L, HL,
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ADash, FlagsDash, AFDash,
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BDash, CDash, BCDash,
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DDash, EDash, DEDash,
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HDash, LDash, HLDash,
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IXh, IXl, IX,
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IYh, IYl, IY,
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R, I, Refresh,
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IFF1, IFF2, IM,
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MemPtr
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};
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/*
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Flags as defined on the Z80; can be used to decode the result of getting or setting @c Flags.
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*/
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enum Flag: uint8_t {
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Sign = 0x80,
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Zero = 0x40,
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Bit5 = 0x20,
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HalfCarry = 0x10,
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Bit3 = 0x08,
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Parity = 0x04,
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Overflow = 0x04,
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Subtract = 0x02,
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Carry = 0x01
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};
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/*!
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Subclasses will be given the task of performing partial machine cycles, allowing them to provide whatever interface they like
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between a Z80 and the rest of the system. @c PartialMachineCycle defines the information they will be handed for each unit
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of execution.
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*/
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struct PartialMachineCycle {
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enum Operation {
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/// The final half cycle of the opcode fetch part of an M1 cycle.
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ReadOpcode = 0,
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/// The 1.5 cycles of a read cycle.
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Read,
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/// The 1.5 cycles of a write cycle.
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Write,
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/// The 1.5 cycles of an input cycle.
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Input,
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/// The 1.5 cycles of an output cycle.
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Output,
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/// The 1.5 cycles of an interrupt acknowledgment.
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Interrupt,
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/// The two-cycle refresh part of an M1 cycle.
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Refresh,
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/// A period with no changes in bus signalling.
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Internal,
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/// A bus acknowledgement cycle.
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BusAcknowledge,
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/// A wait state within an M1 cycle.
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ReadOpcodeWait,
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/// A wait state within a read cycle.
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ReadWait,
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/// A wait state within a write cycle.
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WriteWait,
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/// A wait state within an input cycle.
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InputWait,
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/// A wait state within an output cycle.
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OutputWait,
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/// A wait state within an interrupt acknowledge cycle.
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InterruptWait,
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/// The first 1.5 cycles of an M1 bus cycle, up to the sampling of WAIT.
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ReadOpcodeStart,
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/// The first 1.5 cycles of a read cycle, up to the sampling of WAIT.
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ReadStart,
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/// The first 1.5 cycles of a write cycle, up to the sampling of WAIT.
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WriteStart,
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/// The first 1.5 samples of an input bus cycle, up to the sampling of WAIT.
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InputStart,
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/// The first 1.5 samples of an output bus cycle, up to the sampling of WAIT.
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OutputStart,
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/// The first portion of an interrupt acknowledgement — 2.5 or 3.5 cycles, depending on interrupt mode.
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InterruptStart,
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};
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/// The operation being carried out by the Z80. See the various getters below for better classification.
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const Operation operation = Operation::Internal;
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/// The length of this operation.
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const HalfCycles length;
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/// The current value of the address bus.
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const uint16_t *const address = nullptr;
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/// If the Z80 is outputting to the data bus, a pointer to that value. Otherwise, a pointer to the location where the current data bus value should be placed.
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uint8_t *const value = nullptr;
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/// @c true if this operation is occurring only because of an external request; @c false otherwise.
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const bool was_requested = false;
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/*!
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@returns @c true if the processor believes that the bus handler should actually do something with
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the content of this PartialMachineCycle; @c false otherwise.
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*/
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forceinline bool expects_action() const {
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return operation <= Operation::Interrupt;
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}
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/*!
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@returns @c true if this partial machine cycle completes one of the documented full machine cycles;
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@c false otherwise.
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*/
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forceinline bool is_terminal() const {
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return operation <= Operation::BusAcknowledge;
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}
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/*!
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@returns @c true if this partial machine cycle is a wait cycle; @c false otherwise.
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*/
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forceinline bool is_wait() const {
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return operation >= Operation::ReadOpcodeWait && operation <= Operation::InterruptWait;
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}
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enum Line {
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CLK = 1 << 0,
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MREQ = 1 << 1,
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IOREQ = 1 << 2,
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RD = 1 << 3,
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WR = 1 << 4,
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RFSH = 1 << 5,
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M1 = 1 << 6,
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BUSACK = 1 << 7,
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};
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/// @returns A C-style array of the bus state at the beginning of each half cycle in this
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/// partial machine cycle. Each element is a combination of bit masks from the Line enum;
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/// bit set means line active, bit clear means line inactive. For the CLK line set means high.
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///
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/// @discussion This discrete sampling is prone to aliasing errors. Beware.
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const uint8_t *bus_state() const {
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switch(operation) {
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//
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// M1 cycle
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//
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case Operation::ReadOpcodeStart: {
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static constexpr uint8_t states[] = {
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Line::CLK | Line::M1,
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Line::M1 | Line::MREQ | Line::RD,
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Line::CLK | Line::M1 | Line::MREQ | Line::RD,
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};
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return states;
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}
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case Operation::ReadOpcode:
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case Operation::ReadOpcodeWait: {
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static constexpr uint8_t states[] = {
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Line::M1 | Line::MREQ | Line::RD,
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Line::CLK | Line::M1 | Line::MREQ | Line::RD,
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};
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return states;
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}
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case Operation::Refresh: {
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static constexpr uint8_t states[] = {
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Line::CLK | Line::RFSH | Line::MREQ,
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Line::RFSH,
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Line::CLK | Line::RFSH | Line::MREQ,
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Line::RFSH | Line::MREQ,
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Line::CLK | Line::RFSH,
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Line::RFSH,
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Line::CLK | Line::RFSH,
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Line::RFSH,
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};
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return states;
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}
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//
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// Read cycle.
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//
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case Operation::ReadStart: {
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static constexpr uint8_t states[] = {
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Line::CLK,
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Line::RD | Line::MREQ,
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Line::CLK | Line::RD | Line::MREQ,
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};
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return states;
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}
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case Operation::ReadWait: {
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static constexpr uint8_t states[] = {
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Line::MREQ | Line::RD,
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Line::CLK | Line::MREQ | Line::RD,
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Line::MREQ | Line::RD,
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Line::CLK | Line::MREQ | Line::RD,
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Line::MREQ | Line::RD,
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Line::CLK | Line::MREQ | Line::RD,
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};
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return states;
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}
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case Operation::Read: {
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static constexpr uint8_t states[] = {
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Line::MREQ | Line::RD,
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Line::CLK | Line::MREQ | Line::RD,
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0,
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};
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return states;
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}
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//
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// Write cycle.
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//
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case Operation::WriteStart: {
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static constexpr uint8_t states[] = {
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Line::CLK,
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Line::MREQ,
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Line::CLK | Line::MREQ,
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};
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return states;
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}
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case Operation::WriteWait: {
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static constexpr uint8_t states[] = {
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Line::MREQ,
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Line::CLK | Line::MREQ,
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Line::MREQ,
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Line::CLK | Line::MREQ,
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Line::MREQ,
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Line::CLK | Line::MREQ,
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};
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return states;
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}
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case Operation::Write: {
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static constexpr uint8_t states[] = {
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Line::MREQ | Line::WR,
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Line::CLK | Line::MREQ | Line::WR,
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0,
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};
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return states;
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}
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//
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// Input cycle.
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//
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case Operation::InputStart: {
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static constexpr uint8_t states[] = {
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Line::CLK,
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0,
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Line::CLK | Line::IOREQ | Line::RD,
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};
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return states;
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}
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case Operation::InputWait: {
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static constexpr uint8_t states[] = {
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Line::IOREQ | Line::RD,
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Line::CLK | Line::IOREQ | Line::RD,
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};
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return states;
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}
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case Operation::Input: {
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static constexpr uint8_t states[] = {
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Line::IOREQ | Line::RD,
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Line::CLK | Line::IOREQ | Line::RD,
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0,
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};
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return states;
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}
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//
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// Output cycle.
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//
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case Operation::OutputStart: {
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static constexpr uint8_t states[] = {
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Line::CLK,
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0,
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Line::CLK | Line::IOREQ | Line::WR,
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};
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return states;
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}
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case Operation::OutputWait: {
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static constexpr uint8_t states[] = {
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Line::IOREQ | Line::WR,
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Line::CLK | Line::IOREQ | Line::WR,
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};
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return states;
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}
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case Operation::Output: {
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static constexpr uint8_t states[] = {
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Line::IOREQ | Line::WR,
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Line::CLK | Line::IOREQ | Line::WR,
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0,
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};
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return states;
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}
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//
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// TODO: Interrupt acknowledge.
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//
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//
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// Bus acknowldge.
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//
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case Operation::BusAcknowledge: {
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static constexpr uint8_t states[] = {
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Line::CLK | Line::BUSACK,
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Line::BUSACK,
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};
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return states;
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}
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//
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// Internal.
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//
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case Operation::Internal: {
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static constexpr uint8_t states[] = {
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Line::CLK, 0,
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Line::CLK, 0,
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Line::CLK, 0,
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Line::CLK, 0,
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Line::CLK, 0,
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};
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return states;
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}
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default: break;
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}
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return nullptr;
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}
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PartialMachineCycle(const PartialMachineCycle &rhs) noexcept;
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PartialMachineCycle(Operation operation, HalfCycles length, uint16_t *address, uint8_t *value, bool was_requested) noexcept;
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PartialMachineCycle() noexcept;
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};
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/*!
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A class providing empty implementations of the methods a Z80 uses to access the bus. To wire the Z80 to a bus,
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machines should subclass BusHandler and then declare a realisation of the Z80 template, supplying their bus
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handler.
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*/
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class BusHandler {
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public:
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/*!
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Announces that the Z80 has performed the partial machine cycle defined by @c cycle.
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@returns The number of additional HalfCycles that passed in objective time while this Z80 operation was ongoing.
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On an archetypal machine this will be HalfCycles(0) but some architectures may choose not to clock the Z80
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during some periods or may impose wait states so predictably that it's more efficient just to add them
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via this mechanism.
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*/
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HalfCycles perform_machine_cycle([[maybe_unused]] const PartialMachineCycle &cycle) {
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return HalfCycles(0);
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}
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/*!
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Announces completion of all the cycles supplied to a .run_for request on the Z80. Intended to allow
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bus handlers to perform any deferred output work.
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*/
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void flush() {}
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};
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#include "Implementation/Z80Storage.hpp"
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/*!
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A base class from which the Z80 descends; separated for implementation reasons only.
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*/
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class ProcessorBase: public ProcessorStorage {
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public:
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/*!
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Gets the value of a register.
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@see set_value_of_register
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@param r The register to set.
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@returns The value of the register. 8-bit registers will be returned as unsigned.
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*/
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uint16_t get_value_of_register(Register r) const;
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/*!
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Sets the value of a register.
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@see get_value_of_register
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@param r The register to set.
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@param value The value to set. If the register is only 8 bit, the value will be truncated.
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*/
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void set_value_of_register(Register r, uint16_t value);
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/*!
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Gets the value of the HALT output line.
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*/
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inline bool get_halt_line() const;
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/*!
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Sets the logical value of the interrupt line.
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@param offset If called while within perform_machine_cycle this may be a value indicating
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how many cycles before now the line changed state. The value may not be longer than the
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current machine cycle. If called at any other time, this must be zero.
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*/
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inline void set_interrupt_line(bool value, HalfCycles offset = 0);
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/*!
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Gets the value of the interrupt line.
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*/
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inline bool get_interrupt_line() const;
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/*!
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Sets the logical value of the non-maskable interrupt line.
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@param offset See discussion in set_interrupt_line.
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*/
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inline void set_non_maskable_interrupt_line(bool value, HalfCycles offset = 0);
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/*!
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Gets the value of the non-maskable interrupt line.
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*/
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inline bool get_non_maskable_interrupt_line() const;
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/*!
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Sets the logical value of the reset line.
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*/
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inline void set_reset_line(bool value);
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/*!
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Gets whether the Z80 would reset at the next opportunity.
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@returns @c true if the line is logically active; @c false otherwise.
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*/
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bool get_is_resetting() const;
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/*!
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This emulation automatically sets itself up in power-on state at creation, which has the effect of triggering a
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reset at the first opportunity. Use @c reset_power_on to disable that behaviour.
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*/
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void reset_power_on();
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/*!
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@returns @c true if the Z80 is currently beginning to fetch a new instruction; @c false otherwise.
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This is not a speedy operation.
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*/
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bool is_starting_new_instruction() const;
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};
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/*!
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@abstact Template providing emulation of a Z80 processor.
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@discussion Users should provide as the first template parameter a subclass of CPU::Z80::BusHandler; the Z80
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will announce its activity via the bus handler, which is responsible for marrying it to a bus. Users
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can also nominate whether the processor includes support for the bus request and/or wait lines. Declining to
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support either can produce a minor runtime performance improvement.
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*/
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template <class T, bool uses_bus_request, bool uses_wait_line> class Processor: public ProcessorBase {
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public:
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Processor(T &bus_handler);
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/*!
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Runs the Z80 for a supplied number of cycles.
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@discussion Subclasses must implement @c perform_machine_cycle(const PartialMachineCycle &cycle) .
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If it is a read operation then @c value will be seeded with the value 0xff.
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@param cycles The number of cycles to run for.
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*/
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void run_for(const HalfCycles cycles);
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/*!
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Sets the logical value of the bus request line, having asserted that this Z80 supports the bus request line.
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*/
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void set_bus_request_line(bool value);
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/*!
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Gets the logical value of the bus request line.
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*/
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bool get_bus_request_line() const;
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/*!
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Sets the logical value of the wait line, having asserted that this Z80 supports the wait line.
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*/
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void set_wait_line(bool value);
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/*!
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Gets the logical value of the bus request line.
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*/
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bool get_wait_line() const;
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private:
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T &bus_handler_;
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void assemble_page(InstructionPage &target, InstructionTable &table, bool add_offsets);
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void copy_program(const MicroOp *source, std::vector<MicroOp> &destination);
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};
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#include "Implementation/Z80Implementation.hpp"
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}
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}
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#endif /* Z80_hpp */
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