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675 lines
22 KiB
C++
675 lines
22 KiB
C++
//
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// Z80.cpp
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// Clock Signal
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//
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// Created by Thomas Harte on 30/12/2017.
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// Copyright 2017 Thomas Harte. All rights reserved.
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//
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#include "Z80.hpp"
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#include "Kernel.hpp"
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using namespace Analyser::Static::Z80;
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namespace {
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using PartialDisassembly = Analyser::Static::Disassembly::PartialDisassembly<Disassembly, uint16_t>;
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class Accessor {
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public:
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Accessor(
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const std::vector<uint8_t> &memory,
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const std::function<std::size_t(uint16_t)> &address_mapper,
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uint16_t address
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) :
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memory_(memory), address_mapper_(address_mapper), address_(address) {}
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uint8_t byte() {
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std::size_t mapped_address = address_mapper_(address_);
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++address_;
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if(mapped_address >= memory_.size()) {
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overrun_ = true;
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return 0xff;
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}
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return memory_[mapped_address];
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}
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uint16_t word() {
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uint8_t low = byte();
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uint8_t high = byte();
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return uint16_t(low | (high << 8));
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}
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bool overrun() const {
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return overrun_;
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}
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bool at_end() const {
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std::size_t mapped_address = address_mapper_(address_);
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return mapped_address >= memory_.size();
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}
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uint16_t address() const {
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return address_;
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}
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private:
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const std::vector<uint8_t> &memory_;
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const std::function<std::size_t(uint16_t)> &address_mapper_;
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uint16_t address_;
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bool overrun_ = false;
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};
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constexpr uint8_t x(uint8_t v) { return v >> 6; }
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constexpr uint8_t y(uint8_t v) { return (v >> 3) & 7; }
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constexpr uint8_t q(uint8_t v) { return (v >> 3) & 1; }
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constexpr uint8_t p(uint8_t v) { return (v >> 4) & 3; }
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constexpr uint8_t z(uint8_t v) { return v & 7; }
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Instruction::Condition condition_table[] = {
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Instruction::Condition::NZ, Instruction::Condition::Z,
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Instruction::Condition::NC, Instruction::Condition::C,
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Instruction::Condition::PO, Instruction::Condition::PE,
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Instruction::Condition::P, Instruction::Condition::M
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};
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Instruction::Location register_pair_table[] = {
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Instruction::Location::BC,
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Instruction::Location::DE,
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Instruction::Location::HL,
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Instruction::Location::SP
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};
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Instruction::Location register_pair_table2[] = {
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Instruction::Location::BC,
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Instruction::Location::DE,
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Instruction::Location::HL,
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Instruction::Location::AF
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};
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Instruction::Location RegisterTableEntry(
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const int offset, Accessor &accessor,
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Instruction &instruction,
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const bool needs_indirect_offset
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) {
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constexpr Instruction::Location register_table[] = {
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Instruction::Location::B, Instruction::Location::C,
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Instruction::Location::D, Instruction::Location::E,
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Instruction::Location::H, Instruction::Location::L,
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Instruction::Location::HL_Indirect,
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Instruction::Location::A
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};
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const Instruction::Location location = register_table[offset];
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if(location == Instruction::Location::HL_Indirect && needs_indirect_offset) {
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instruction.offset = accessor.byte() - 128;
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}
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return location;
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}
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constexpr Instruction::Operation alu_table[] = {
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Instruction::Operation::ADD,
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Instruction::Operation::ADC,
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Instruction::Operation::SUB,
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Instruction::Operation::SBC,
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Instruction::Operation::AND,
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Instruction::Operation::XOR,
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Instruction::Operation::OR,
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Instruction::Operation::CP
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};
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constexpr Instruction::Operation rotation_table[] = {
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Instruction::Operation::RLC,
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Instruction::Operation::RRC,
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Instruction::Operation::RL,
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Instruction::Operation::RR,
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Instruction::Operation::SLA,
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Instruction::Operation::SRA,
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Instruction::Operation::SLL,
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Instruction::Operation::SRL
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};
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constexpr Instruction::Operation block_table[][4] = {
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{
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Instruction::Operation::LDI, Instruction::Operation::CPI,
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Instruction::Operation::INI, Instruction::Operation::OUTI
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},
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{
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Instruction::Operation::LDD, Instruction::Operation::CPD,
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Instruction::Operation::IND, Instruction::Operation::OUTD
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},
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{
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Instruction::Operation::LDIR, Instruction::Operation::CPIR,
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Instruction::Operation::INIR, Instruction::Operation::OTIR
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},
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{
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Instruction::Operation::LDDR, Instruction::Operation::CPDR,
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Instruction::Operation::INDR, Instruction::Operation::OTDR
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},
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};
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void DisassembleCBPage(Accessor &accessor, Instruction &instruction, const bool needs_indirect_offset) {
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const uint8_t operation = accessor.byte();
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if(!x(operation)) {
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instruction.operation = rotation_table[y(operation)];
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instruction.source = instruction.destination =
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RegisterTableEntry(z(operation), accessor, instruction, needs_indirect_offset);
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} else {
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instruction.destination = RegisterTableEntry(z(operation), accessor, instruction, needs_indirect_offset);
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instruction.source = Instruction::Location::Operand;
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instruction.operand = y(operation);
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switch(x(operation)) {
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case 1: instruction.operation = Instruction::Operation::BIT; break;
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case 2: instruction.operation = Instruction::Operation::RES; break;
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case 3: instruction.operation = Instruction::Operation::SET; break;
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}
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}
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}
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void DisassembleEDPage(Accessor &accessor, Instruction &instruction, const bool needs_indirect_offset) {
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const uint8_t operation = accessor.byte();
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switch(x(operation)) {
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default:
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instruction.operation = Instruction::Operation::Invalid;
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break;
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case 2:
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if(z(operation) < 4 && y(operation) >= 4) {
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instruction.operation = block_table[y(operation)-4][z(operation)];
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} else {
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instruction.operation = Instruction::Operation::Invalid;
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}
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break;
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case 3:
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switch(z(operation)) {
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case 0:
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instruction.operation = Instruction::Operation::IN;
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instruction.source = Instruction::Location::BC_Indirect;
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if(y(operation) == 6) {
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instruction.destination = Instruction::Location::None;
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} else {
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instruction.destination =
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RegisterTableEntry(y(operation), accessor, instruction, needs_indirect_offset);
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}
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break;
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case 1:
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instruction.operation = Instruction::Operation::OUT;
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instruction.destination = Instruction::Location::BC_Indirect;
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if(y(operation) == 6) {
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instruction.source = Instruction::Location::None;
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} else {
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instruction.source =
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RegisterTableEntry(y(operation), accessor, instruction, needs_indirect_offset);
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}
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break;
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case 2:
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instruction.operation = (y(operation)&1) ? Instruction::Operation::ADC : Instruction::Operation::SBC;
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instruction.destination = Instruction::Location::HL;
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instruction.source = register_pair_table[y(operation) >> 1];
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break;
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case 3:
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instruction.operation = Instruction::Operation::LD;
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if(q(operation)) {
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instruction.destination =
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RegisterTableEntry(p(operation), accessor, instruction, needs_indirect_offset);
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instruction.source = Instruction::Location::Operand_Indirect;
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} else {
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instruction.destination = Instruction::Location::Operand_Indirect;
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instruction.source =
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RegisterTableEntry(p(operation), accessor, instruction, needs_indirect_offset);
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}
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instruction.operand = accessor.word();
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break;
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case 4:
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instruction.operation = Instruction::Operation::NEG;
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break;
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case 5:
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instruction.operation =
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y(operation) == 1 ? Instruction::Operation::RETI : Instruction::Operation::RETN;
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break;
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case 6:
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instruction.operation = Instruction::Operation::IM;
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instruction.source = Instruction::Location::Operand;
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switch(y(operation)&3) {
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case 0: instruction.operand = 0; break;
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case 1: instruction.operand = 0; break;
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case 2: instruction.operand = 1; break;
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case 3: instruction.operand = 2; break;
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}
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break;
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case 7:
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switch(y(operation)) {
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case 0:
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instruction.operation = Instruction::Operation::LD;
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instruction.destination = Instruction::Location::I;
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instruction.source = Instruction::Location::A;
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break;
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case 1:
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instruction.operation = Instruction::Operation::LD;
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instruction.destination = Instruction::Location::R;
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instruction.source = Instruction::Location::A;
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break;
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case 2:
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instruction.operation = Instruction::Operation::LD;
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instruction.destination = Instruction::Location::A;
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instruction.source = Instruction::Location::I;
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break;
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case 3:
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instruction.operation = Instruction::Operation::LD;
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instruction.destination = Instruction::Location::A;
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instruction.source = Instruction::Location::R;
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break;
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case 4: instruction.operation = Instruction::Operation::RRD; break;
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case 5: instruction.operation = Instruction::Operation::RLD; break;
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default: instruction.operation = Instruction::Operation::NOP; break;
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}
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break;
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}
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break;
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}
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}
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void DisassembleMainPage(Accessor &accessor, Instruction &instruction) {
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bool needs_indirect_offset = false;
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enum HLSubstitution {
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None, IX, IY
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} hl_substitution = None;
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while(true) {
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const uint8_t operation = accessor.byte();
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switch(x(operation)) {
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case 0:
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switch(z(operation)) {
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case 0:
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switch(y(operation)) {
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case 0: instruction.operation = Instruction::Operation::NOP; break;
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case 1: instruction.operation = Instruction::Operation::EXAFAFd; break;
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case 2:
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instruction.operation = Instruction::Operation::DJNZ;
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instruction.operand = accessor.byte() - 128;
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break;
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default:
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instruction.operation = Instruction::Operation::JR;
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instruction.operand = accessor.byte() - 128;
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if(y(operation) >= 4) instruction.condition = condition_table[y(operation) - 4];
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break;
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}
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break;
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case 1:
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if(y(operation)&1) {
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instruction.operation = Instruction::Operation::ADD;
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instruction.destination = Instruction::Location::HL;
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instruction.source = register_pair_table[y(operation) >> 1];
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} else {
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instruction.operation = Instruction::Operation::LD;
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instruction.destination = register_pair_table[y(operation) >> 1];
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instruction.source = Instruction::Location::Operand;
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instruction.operand = accessor.word();
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}
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break;
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case 2:
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switch(y(operation)) {
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case 0:
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instruction.operation = Instruction::Operation::LD;
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instruction.destination = Instruction::Location::BC_Indirect;
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instruction.source = Instruction::Location::A;
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break;
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case 1:
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instruction.operation = Instruction::Operation::LD;
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instruction.destination = Instruction::Location::A;
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instruction.source = Instruction::Location::BC_Indirect;
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break;
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case 2:
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instruction.operation = Instruction::Operation::LD;
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instruction.destination = Instruction::Location::DE_Indirect;
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instruction.source = Instruction::Location::A;
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break;
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case 3:
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instruction.operation = Instruction::Operation::LD;
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instruction.destination = Instruction::Location::A;
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instruction.source = Instruction::Location::DE_Indirect;
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break;
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case 4:
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instruction.operation = Instruction::Operation::LD;
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instruction.destination = Instruction::Location::Operand_Indirect;
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instruction.source = Instruction::Location::HL;
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break;
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case 5:
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instruction.operation = Instruction::Operation::LD;
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instruction.destination = Instruction::Location::HL;
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instruction.source = Instruction::Location::Operand_Indirect;
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break;
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case 6:
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instruction.operation = Instruction::Operation::LD;
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instruction.destination = Instruction::Location::Operand_Indirect;
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instruction.source = Instruction::Location::A;
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break;
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case 7:
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instruction.operation = Instruction::Operation::LD;
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instruction.destination = Instruction::Location::A;
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instruction.source = Instruction::Location::Operand_Indirect;
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break;
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}
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if(y(operation) > 3) {
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instruction.operand = accessor.word();
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}
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break;
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case 3:
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if(y(operation)&1) {
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instruction.operation = Instruction::Operation::DEC;
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} else {
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instruction.operation = Instruction::Operation::INC;
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}
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instruction.source = instruction.destination = register_pair_table[y(operation) >> 1];
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break;
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case 4:
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instruction.operation = Instruction::Operation::INC;
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instruction.source = instruction.destination =
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RegisterTableEntry(y(operation), accessor, instruction, needs_indirect_offset);
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break;
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case 5:
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instruction.operation = Instruction::Operation::DEC;
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instruction.source = instruction.destination =
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RegisterTableEntry(y(operation), accessor, instruction, needs_indirect_offset);
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break;
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case 6:
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instruction.operation = Instruction::Operation::LD;
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instruction.destination =
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RegisterTableEntry(y(operation), accessor, instruction, needs_indirect_offset);
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instruction.source = Instruction::Location::Operand;
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instruction.operand = accessor.byte();
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break;
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case 7:
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switch(y(operation)) {
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case 0: instruction.operation = Instruction::Operation::RLCA; break;
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case 1: instruction.operation = Instruction::Operation::RRCA; break;
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case 2: instruction.operation = Instruction::Operation::RLA; break;
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case 3: instruction.operation = Instruction::Operation::RRA; break;
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case 4: instruction.operation = Instruction::Operation::DAA; break;
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case 5: instruction.operation = Instruction::Operation::CPL; break;
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case 6: instruction.operation = Instruction::Operation::SCF; break;
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case 7: instruction.operation = Instruction::Operation::CCF; break;
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}
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break;
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}
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break;
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case 1:
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if(y(operation) == 6 && z(operation) == 6) {
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instruction.operation = Instruction::Operation::HALT;
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} else {
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instruction.operation = Instruction::Operation::LD;
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instruction.source =
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RegisterTableEntry(z(operation), accessor, instruction, needs_indirect_offset);
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instruction.destination =
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RegisterTableEntry(y(operation), accessor, instruction, needs_indirect_offset);
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}
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break;
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case 2:
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instruction.operation = alu_table[y(operation)];
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instruction.source = RegisterTableEntry(z(operation), accessor, instruction, needs_indirect_offset);
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instruction.destination = Instruction::Location::A;
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break;
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case 3:
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switch(z(operation)) {
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case 0:
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instruction.operation = Instruction::Operation::RET;
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instruction.condition = condition_table[y(operation)];
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break;
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case 1:
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switch(y(operation)) {
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default:
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instruction.operation = Instruction::Operation::POP;
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instruction.source = register_pair_table2[y(operation) >> 1];
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break;
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case 1:
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instruction.operation = Instruction::Operation::RET;
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break;
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case 3:
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instruction.operation = Instruction::Operation::EXX;
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break;
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case 5:
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instruction.operation = Instruction::Operation::JP;
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instruction.source = Instruction::Location::HL;
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break;
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case 7:
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instruction.operation = Instruction::Operation::LD;
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instruction.destination = Instruction::Location::SP;
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instruction.source = Instruction::Location::HL;
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break;
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}
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break;
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case 2:
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instruction.operation = Instruction::Operation::JP;
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instruction.condition = condition_table[y(operation)];
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instruction.operand = accessor.word();
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break;
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case 3:
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switch(y(operation)) {
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case 0:
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instruction.operation = Instruction::Operation::JP;
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instruction.source = Instruction::Location::Operand;
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instruction.operand = accessor.word();
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break;
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case 1:
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DisassembleCBPage(accessor, instruction, needs_indirect_offset);
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break;
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case 2:
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instruction.operation = Instruction::Operation::OUT;
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instruction.source = Instruction::Location::A;
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instruction.destination = Instruction::Location::Operand_Indirect;
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instruction.operand = accessor.byte();
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break;
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case 3:
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instruction.operation = Instruction::Operation::IN;
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instruction.destination = Instruction::Location::A;
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instruction.source = Instruction::Location::Operand_Indirect;
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instruction.operand = accessor.byte();
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break;
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case 4:
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instruction.operation = Instruction::Operation::EX;
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instruction.destination = Instruction::Location::SP_Indirect;
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instruction.source = Instruction::Location::HL;
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break;
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case 5:
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instruction.operation = Instruction::Operation::EX;
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instruction.destination = Instruction::Location::DE;
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instruction.source = Instruction::Location::HL;
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break;
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case 6:
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instruction.operation = Instruction::Operation::DI;
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break;
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case 7:
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instruction.operation = Instruction::Operation::EI;
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break;
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}
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break;
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case 4:
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instruction.operation = Instruction::Operation::CALL;
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instruction.source = Instruction::Location::Operand_Indirect;
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instruction.operand = accessor.word();
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instruction.condition = condition_table[y(operation)];
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break;
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case 5:
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switch(y(operation)) {
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default:
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instruction.operation = Instruction::Operation::PUSH;
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instruction.source = register_pair_table2[y(operation) >> 1];
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break;
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case 1:
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instruction.operation = Instruction::Operation::CALL;
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instruction.source = Instruction::Location::Operand;
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instruction.operand = accessor.word();
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break;
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case 3:
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needs_indirect_offset = true;
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hl_substitution = IX;
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continue; // i.e. repeat loop.
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case 5:
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DisassembleEDPage(accessor, instruction, needs_indirect_offset);
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break;
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case 7:
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needs_indirect_offset = true;
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hl_substitution = IY;
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continue; // i.e. repeat loop.
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}
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break;
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case 6:
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instruction.operation = alu_table[y(operation)];
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instruction.source = Instruction::Location::Operand;
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instruction.destination = Instruction::Location::A;
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instruction.operand = accessor.byte();
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break;
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case 7:
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instruction.operation = Instruction::Operation::RST;
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instruction.source = Instruction::Location::Operand;
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instruction.operand = y(operation) << 3;
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
|
|
// This while(true) isn't an infinite loop for everything except those paths that opt in
|
|
// via continue.
|
|
break;
|
|
}
|
|
|
|
// Perform IX/IY substitution for HL, if applicable.
|
|
if(hl_substitution != None) {
|
|
// EX DE, HL is not affected.
|
|
if(instruction.operation == Instruction::Operation::EX) return;
|
|
|
|
// If an (HL) is involved, switch it for IX+d or IY+d.
|
|
if( instruction.source == Instruction::Location::HL_Indirect ||
|
|
instruction.destination == Instruction::Location::HL_Indirect) {
|
|
|
|
if(instruction.source == Instruction::Location::HL_Indirect) {
|
|
instruction.source =
|
|
hl_substitution == IX ?
|
|
Instruction::Location::IX_Indirect_Offset : Instruction::Location::IY_Indirect_Offset;
|
|
}
|
|
if(instruction.destination == Instruction::Location::HL_Indirect) {
|
|
instruction.destination =
|
|
hl_substitution == IX ?
|
|
Instruction::Location::IX_Indirect_Offset : Instruction::Location::IY_Indirect_Offset;
|
|
}
|
|
return;
|
|
}
|
|
|
|
// Otherwise, switch either of H or L for I[X/Y]h and I[X/Y]l.
|
|
if(instruction.source == Instruction::Location::H) {
|
|
instruction.source = (hl_substitution == IX) ? Instruction::Location::IXh : Instruction::Location::IYh;
|
|
}
|
|
if(instruction.source == Instruction::Location::L) {
|
|
instruction.source = (hl_substitution == IX) ? Instruction::Location::IXl : Instruction::Location::IYl;
|
|
}
|
|
if(instruction.destination == Instruction::Location::H) {
|
|
instruction.destination = (hl_substitution == IX) ? Instruction::Location::IXh : Instruction::Location::IYh;
|
|
}
|
|
if(instruction.destination == Instruction::Location::L) {
|
|
instruction.destination = (hl_substitution == IX) ? Instruction::Location::IXl : Instruction::Location::IYl;
|
|
}
|
|
}
|
|
}
|
|
|
|
struct Z80Disassembler {
|
|
static void AddToDisassembly(
|
|
PartialDisassembly &disassembly,
|
|
const std::vector<uint8_t> &memory,
|
|
const std::function<std::size_t(uint16_t)> &address_mapper,
|
|
const uint16_t entry_point
|
|
) {
|
|
disassembly.disassembly.internal_calls.insert(entry_point);
|
|
Accessor accessor(memory, address_mapper, entry_point);
|
|
|
|
while(!accessor.at_end()) {
|
|
Instruction instruction;
|
|
instruction.address = accessor.address();
|
|
|
|
DisassembleMainPage(accessor, instruction);
|
|
|
|
// If any memory access was invalid, end disassembly.
|
|
if(accessor.overrun()) return;
|
|
|
|
// Store the instruction away.
|
|
disassembly.disassembly.instructions_by_address[instruction.address] = instruction;
|
|
|
|
// Update access tables.
|
|
int access_type =
|
|
((instruction.source == Instruction::Location::Operand_Indirect) ? 1 : 0) |
|
|
((instruction.destination == Instruction::Location::Operand_Indirect) ? 2 : 0);
|
|
uint16_t address = uint16_t(instruction.operand);
|
|
bool is_internal = address_mapper(address) < memory.size();
|
|
switch(access_type) {
|
|
default: break;
|
|
case 1:
|
|
if(is_internal) {
|
|
disassembly.disassembly.internal_loads.insert(address);
|
|
} else {
|
|
disassembly.disassembly.external_loads.insert(address);
|
|
}
|
|
break;
|
|
case 2:
|
|
if(is_internal) {
|
|
disassembly.disassembly.internal_stores.insert(address);
|
|
} else {
|
|
disassembly.disassembly.external_stores.insert(address);
|
|
}
|
|
break;
|
|
case 3:
|
|
if(is_internal) {
|
|
disassembly.disassembly.internal_modifies.insert(address);
|
|
} else {
|
|
disassembly.disassembly.internal_modifies.insert(address);
|
|
}
|
|
break;
|
|
}
|
|
|
|
// Add any (potentially) newly-discovered entry point.
|
|
if( instruction.operation == Instruction::Operation::JP ||
|
|
instruction.operation == Instruction::Operation::JR ||
|
|
instruction.operation == Instruction::Operation::CALL ||
|
|
instruction.operation == Instruction::Operation::RST) {
|
|
disassembly.remaining_entry_points.push_back(uint16_t(instruction.operand));
|
|
}
|
|
|
|
// This is it if: an unconditional RET, RETI, RETN, JP or JR is found.
|
|
switch(instruction.operation) {
|
|
default: break;
|
|
|
|
case Instruction::Operation::RET:
|
|
case Instruction::Operation::RETI:
|
|
case Instruction::Operation::RETN:
|
|
case Instruction::Operation::JP:
|
|
case Instruction::Operation::JR:
|
|
if(instruction.condition == Instruction::Condition::None) {
|
|
disassembly.implicit_entry_points.push_back(accessor.address());
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
};
|
|
|
|
} // end of anonymous namespace
|
|
|
|
|
|
|
|
Disassembly Analyser::Static::Z80::Disassemble(
|
|
const std::vector<uint8_t> &memory,
|
|
const std::function<std::size_t(uint16_t)> &address_mapper,
|
|
std::vector<uint16_t> entry_points,
|
|
Approach approach)
|
|
{
|
|
return Analyser::Static::Disassembly::Disassemble<Disassembly, uint16_t, Z80Disassembler>(
|
|
memory,
|
|
address_mapper,
|
|
entry_points,
|
|
approach == Approach::Exhaustive
|
|
);
|
|
}
|