mirror of
https://github.com/TomHarte/CLK.git
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142 lines
3.4 KiB
C++
142 lines
3.4 KiB
C++
//
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// Status.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 25/02/2024.
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// Copyright © 2024 Thomas Harte. All rights reserved.
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//
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#pragma once
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#include "OperationMapper.hpp"
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#include <cstdint>
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namespace InstructionSet::ARM {
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namespace ConditionCode {
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static constexpr uint32_t Negative = 1 << 31;
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static constexpr uint32_t Zero = 1 << 30;
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static constexpr uint32_t Carry = 1 << 29;
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static constexpr uint32_t Overflow = 1 << 28;
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static constexpr uint32_t IRQDisable = 1 << 27;
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static constexpr uint32_t FIQDisable = 1 << 26;
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static constexpr uint32_t Mode = (1 << 1) | (1 << 0);
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static constexpr uint32_t Address = FIQDisable - Mode - 1;
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}
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enum class Mode {
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User = 0b00,
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FIQ = 0b01,
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IRQ = 0b10,
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Supervisor = 0b11,
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};
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struct Status {
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public:
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/// Sets the N and Z flags according to the value of @c result.
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void set_nz(uint32_t value) {
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zero_result_ = negative_flag_ = value;
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}
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/// Sets C if @c value is non-zero; resets it otherwise.
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void set_c(uint32_t value) {
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carry_flag_ = value;
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}
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/// @returns @c 1 if carry is set; @c 0 otherwise.
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uint32_t c() const {
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return carry_flag_ ? 1 : 0;
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}
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/// Sets V if the highest bit of @c value is set; resets it otherwise.
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void set_v(uint32_t value) {
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overflow_flag_ = value;
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}
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/// @returns The program counter address only, optionally with a post-increment.
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template <bool increment>
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uint32_t pc() {
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const uint32_t result = pc_;
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if constexpr (increment) {
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pc_ = (pc_ + 4) & ConditionCode::Address;
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}
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return result;
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}
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void begin_irq() { interrupt_flags_ |= ConditionCode::IRQDisable; }
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void begin_fiq() { interrupt_flags_ |= ConditionCode::FIQDisable; }
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/// @returns The full PC + status bits.
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uint32_t get() const {
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return
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uint32_t(mode_) |
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pc_ |
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(negative_flag_ & ConditionCode::Negative) |
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(zero_result_ ? 0 : ConditionCode::Zero) |
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(carry_flag_ ? ConditionCode::Carry : 0) |
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((overflow_flag_ >> 3) & ConditionCode::Overflow) |
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interrupt_flags_;
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}
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bool test(Condition condition) {
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const auto ne = [&]() -> bool {
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return zero_result_;
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};
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const auto cs = [&]() -> bool {
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return carry_flag_;
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};
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const auto mi = [&]() -> bool {
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return negative_flag_ & ConditionCode::Negative;
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};
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const auto vs = [&]() -> bool {
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return overflow_flag_ & ConditionCode::Negative;
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};
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const auto hi = [&]() -> bool {
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return carry_flag_ && zero_result_;
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};
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const auto lt = [&]() -> bool {
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return (negative_flag_ ^ overflow_flag_) & ConditionCode::Negative;
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};
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const auto le = [&]() -> bool {
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return !zero_result_ || lt();
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};
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switch(condition) {
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case Condition::EQ: return !ne();
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case Condition::NE: return ne();
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case Condition::CS: return cs();
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case Condition::CC: return !cs();
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case Condition::MI: return mi();
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case Condition::PL: return !mi();
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case Condition::VS: return vs();
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case Condition::VC: return !vs();
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case Condition::HI: return hi();
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case Condition::LS: return !hi();
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case Condition::GE: return !lt();
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case Condition::LT: return lt();
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case Condition::GT: return !le();
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case Condition::LE: return le();
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case Condition::AL: return true;
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case Condition::NV: return false;
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}
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}
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private:
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uint32_t pc_ = 0;
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Mode mode_ = Mode::Supervisor;
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uint32_t zero_result_ = 0;
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uint32_t negative_flag_ = 0;
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uint32_t interrupt_flags_ = 0;
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uint32_t carry_flag_ = 0;
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uint32_t overflow_flag_ = 0;
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};
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}
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