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228 lines
6.3 KiB
C++
228 lines
6.3 KiB
C++
//
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// DMAController.cpp
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// Clock Signal
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//
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// Created by Thomas Harte on 26/10/2019.
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// Copyright © 2019 Thomas Harte. All rights reserved.
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//
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#include "DMAController.hpp"
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#include <cstdio>
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using namespace Atari::ST;
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namespace {
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enum Control: uint16_t {
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Direction = 0x100,
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DRQSource = 0x80,
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SectorCountSelect = 0x10,
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CPUTarget = 0x08
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};
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}
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DMAController::DMAController() {
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fdc_.set_delegate(this);
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fdc_.set_clocking_hint_observer(this);
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}
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uint16_t DMAController::read(int address) {
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switch(address & 7) {
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// Reserved.
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default: break;
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// Disk controller or sector count.
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case 2:
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if(control_ & Control::SectorCountSelect) {
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return uint16_t((byte_count_ + 511) >> 9); // Assumed here: the count is of sectors remaining, i.e. it decrements
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// only when a sector is complete.
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} else {
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if(control_ & Control::CPUTarget) {
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return 0xffff;
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} else {
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return 0xff00 | fdc_.get_register(control_ >> 1);
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}
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}
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break;
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// DMA status.
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case 3:
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// TODO: should DRQ come from the HDC if that mode is selected?
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return 0xfff8 | (error_ ? 0 : 1) | (byte_count_ ? 2 : 0) | (fdc_.get_data_request_line() ? 4 : 0);
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// DMA addressing.
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case 4: return uint16_t(0xff00 | ((address_ >> 16) & 0xff));
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case 5: return uint16_t(0xff00 | ((address_ >> 8) & 0xff));
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case 6: return uint16_t(0xff00 | ((address_ >> 0) & 0xff));
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}
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return 0xffff;
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}
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void DMAController::write(int address, uint16_t value) {
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switch(address & 7) {
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// Reserved.
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default: break;
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// Disk controller or sector count.
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case 2:
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if(control_ & Control::SectorCountSelect) {
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byte_count_ = (value & 0xff) << 9; // The computer provides a sector count; that times 512 is a byte count.
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// TODO: if this is a write-mode DMA operation, try to fill both buffers, ASAP.
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} else {
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if(control_ & Control::CPUTarget) {
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// TODO: HDC.
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} else {
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fdc_.set_register(control_ >> 1, uint8_t(value));
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}
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}
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break;
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// DMA control; meaning is:
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//
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// b0: unused
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// b1, b2 = address lines for FDC access.
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// b3 = 1 => CPU HDC access; 0 => CPU FDC access.
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// b4 = 1 => sector count access; 0 => [F/H]DC access.
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// b5: unused.
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// b6 = officially, 1 => DMA off; 0 => DMA on. Ignored in real hardware.
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// b7 = 1 => FDC DRQs being observed; 0 => HDC access DRQs being observed.
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// b8 = 1 => DMA is writing to [F/H]DC; 0 => DMA is reading. Changing value resets DMA state.
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//
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// All other bits: undefined.
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case 3:
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// Check for a DMA state reset.
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if((control_^value) & Control::Direction) {
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bytes_received_ = active_buffer_ = 0;
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error_ = false;
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byte_count_ = 0;
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}
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control_ = value;
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break;
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// DMA addressing.
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case 4: address_ = int((address_ & 0x00ffff) | ((value & 0xff) << 16)); break;
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case 5: address_ = int((address_ & 0xff00ff) | ((value & 0xff) << 8)); break;
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case 6: address_ = int((address_ & 0xffff00) | ((value & 0xff) << 0)); break;
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}
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}
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void DMAController::set_floppy_drive_selection(bool drive1, bool drive2, bool side2) {
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fdc_.set_floppy_drive_selection(drive1, drive2, side2);
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}
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void DMAController::set_floppy_disk(std::shared_ptr<Storage::Disk::Disk> disk, size_t drive) {
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fdc_.drives_[drive]->set_disk(disk);
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}
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void DMAController::run_for(HalfCycles duration) {
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running_time_ += duration;
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fdc_.run_for(duration.flush<Cycles>());
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}
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void DMAController::wd1770_did_change_output(WD::WD1770 *) {
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// Check for a change in interrupt state.
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const bool old_interrupt_line = interrupt_line_;
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interrupt_line_ = fdc_.get_interrupt_request_line();
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if(delegate_ && interrupt_line_ != old_interrupt_line) {
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delegate_->dma_controller_did_change_output(this);
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}
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// Check for a change in DRQ state, if it's the FDC that is currently being watched.
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if(byte_count_ && fdc_.get_data_request_line() && (control_ & Control::DRQSource)) {
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--byte_count_;
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if(control_ & Control::Direction) {
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// TODO: DMA is supposed to be helping with a write.
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} else {
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// DMA is enabling a read.
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// Read from the data register into the active buffer.
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if(bytes_received_ < 16) {
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buffer_[active_buffer_].contents[bytes_received_] = fdc_.get_register(3);
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++bytes_received_;
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}
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if(bytes_received_ == 16) {
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// Mark buffer as full.
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buffer_[active_buffer_].is_full = true;
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// Move to the next if it is empty; if it isn't, note a DMA error.
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const auto next_buffer = active_buffer_ ^ 1;
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error_ |= buffer_[next_buffer].is_full;
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if(!buffer_[next_buffer].is_full) {
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bytes_received_ = 0;
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active_buffer_ = next_buffer;
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}
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// Set bus request.
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if(!bus_request_line_) {
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bus_request_line_ = true;
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if(delegate_) delegate_->dma_controller_did_change_output(this);
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}
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}
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}
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}
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}
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int DMAController::bus_grant(uint16_t *ram, size_t size) {
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// Being granted the bus negates the request.
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bus_request_line_ = false;
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if(delegate_) delegate_->dma_controller_did_change_output(this);
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if(control_ & Control::Direction) {
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// TODO: writes.
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return 0;
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} else {
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// Check that the older buffer is full; stop if not.
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if(!buffer_[active_buffer_ ^ 1].is_full) return 0;
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for(int c = 0; c < 8; ++c) {
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ram[size_t(address_ >> 1) & (size - 1)] = uint16_t(
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(buffer_[active_buffer_ ^ 1].contents[(c << 1) + 0] << 8) |
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(buffer_[active_buffer_ ^ 1].contents[(c << 1) + 1] << 0)
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);
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address_ += 2;
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}
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buffer_[active_buffer_ ^ 1].is_full = false;
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// Check that the newer buffer is full; stop if not.
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if(!buffer_[active_buffer_ ].is_full) return 8;
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for(int c = 0; c < 8; ++c) {
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ram[size_t(address_ >> 1) & (size - 1)] = uint16_t(
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(buffer_[active_buffer_].contents[(c << 1) + 0] << 8) |
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(buffer_[active_buffer_].contents[(c << 1) + 1] << 0)
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);
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address_ += 2;
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}
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buffer_[active_buffer_].is_full = false;
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// Both buffers were full, so unblock reading.
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bytes_received_ = 0;
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return 16;
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}
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}
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void DMAController::set_delegate(Delegate *delegate) {
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delegate_ = delegate;
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}
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bool DMAController::get_interrupt_line() {
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return interrupt_line_;
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}
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bool DMAController::get_bus_request_line() {
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return bus_request_line_;
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}
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void DMAController::set_component_prefers_clocking(ClockingHint::Source *, ClockingHint::Preference) {
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update_clocking_observer();
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}
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ClockingHint::Preference DMAController::preferred_clocking() {
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return (fdc_.preferred_clocking() == ClockingHint::Preference::None) ? ClockingHint::Preference::None : ClockingHint::Preference::RealTime;
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}
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