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455 lines
17 KiB
C++
455 lines
17 KiB
C++
//
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// 68000Mk2.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 16/05/2022.
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// Copyright © 2022 Thomas Harte. All rights reserved.
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//
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#ifndef _8000Mk2_h
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#define _8000Mk2_h
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#include "../../ClockReceiver/ClockReceiver.hpp"
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#include "../../Numeric/RegisterSizes.hpp"
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#include "../../InstructionSets/M68k/RegisterSet.hpp"
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namespace CPU {
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namespace MC68000Mk2 {
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/*!
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A microcycle is an atomic unit of 68000 bus activity — it is a single item large enough
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fully to specify a sequence of bus events that occur without any possible interruption.
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Concretely, a standard read cycle breaks down into at least two microcycles:
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1) a 4 half-cycle length microcycle in which the address strobe is signalled; and
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2) a 4 half-cycle length microcycle in which at least one of the data strobes is
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signalled, and the data bus is sampled.
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That is, assuming DTack were signalled when microcycle (1) ended. If not then additional
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wait state microcycles would fall between those two parts.
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The 68000 data sheet defines when the address becomes valid during microcycle (1), and
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when the address strobe is actually asserted. But those timings are fixed. So simply
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telling you that this was a microcycle during which the address trobe was signalled is
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sufficient fully to describe the bus activity.
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(Aside: see the 68000 template's definition for options re: implicit DTack; if your
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68000 owner can always predict exactly how long it will hold DTack following observation
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of an address-strobing microcycle, it can just supply those periods for accounting and
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avoid the runtime cost of actual DTack emulation. But such as the bus allows.)
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*/
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struct Microcycle {
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using OperationT = unsigned int;
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/// Indicates that the address strobe and exactly one of the data strobes are active; you can determine
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/// which by inspecting the low bit of the provided address. The RW line indicates a read.
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static constexpr OperationT SelectByte = 1 << 0;
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// Maintenance note: this is bit 0 to reduce the cost of getting a host-endian
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// bytewise address. The assumption that it is bit 0 is also used for branchless
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// selection in a few places. See implementation of host_endian_byte_address(),
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// value8_high(), value8_low() and value16().
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/// Indicates that the address and both data select strobes are active.
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static constexpr OperationT SelectWord = 1 << 1;
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/// If set, indicates a read. Otherwise, a write.
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static constexpr OperationT Read = 1 << 2;
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// Two-bit gap deliberately left here for PermitRead/Write below.
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/// A NewAddress cycle is one in which the address strobe is initially low but becomes high;
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/// this correlates to states 0 to 5 of a standard read/write cycle.
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static constexpr OperationT NewAddress = 1 << 5;
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/// A SameAddress cycle is one in which the address strobe is continuously asserted, but neither
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/// of the data strobes are.
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static constexpr OperationT SameAddress = 1 << 6;
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/// A Reset cycle is one in which the RESET output is asserted.
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static constexpr OperationT Reset = 1 << 7;
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/// Contains the value of line FC0 if it is not implicit via InterruptAcknowledge.
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static constexpr OperationT IsData = 1 << 8;
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/// Contains the value of line FC1 if it is not implicit via InterruptAcknowledge.
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static constexpr OperationT IsProgram = 1 << 9;
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/// The interrupt acknowledge cycle is that during which the 68000 seeks to obtain the vector for
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/// an interrupt it plans to observe. Noted on a real 68000 by all FCs being set to 1.
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static constexpr OperationT InterruptAcknowledge = 1 << 10;
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/// Represents the state of the 68000's valid memory address line — indicating whether this microcycle
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/// is synchronised with the E clock to satisfy a valid peripheral address request.
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static constexpr OperationT IsPeripheral = 1 << 11;
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/// Provides the 68000's bus grant line — indicating whether a bus request has been acknowledged.
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static constexpr OperationT BusGrant = 1 << 12;
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/// Contains a valid combination of the various static constexpr int flags, describing the operation
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/// performed by this Microcycle.
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OperationT operation = 0;
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/// Describes the duration of this Microcycle.
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HalfCycles length = HalfCycles(4);
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/*!
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For expediency, this provides a full 32-bit byte-resolution address — e.g.
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if reading indirectly via an address register, this will indicate the full
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value of the address register.
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The receiver should ignore bits 0 and 24+. Use word_address() automatically
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to obtain the only the 68000's real address lines, giving a 23-bit address
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at word resolution.
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*/
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const uint32_t *address = nullptr;
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/*!
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If this is a write cycle, dereference value to get the value loaded onto
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the data bus.
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If this is a read cycle, write the value on the data bus to it.
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Otherwise, this value is undefined.
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If this bus cycle provides a byte then its value is provided via
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@c value->b and @c value->w is undefined. This is true regardless of
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whether the upper or lower byte of a word is being accessed.
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Word values occupy the entirety of @c value->w.
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*/
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SlicedInt16 *value = nullptr;
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Microcycle(OperationT operation) : operation(operation) {}
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Microcycle(OperationT operation, HalfCycles length) : operation(operation), length(length) {}
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Microcycle() {}
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/// @returns @c true if two Microcycles are equal; @c false otherwise.
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bool operator ==(const Microcycle &rhs) const {
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if(value != rhs.value) return false;
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if(address != rhs.address) return false;
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if(length != rhs.length) return false;
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if(operation != rhs.operation) return false;
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return true;
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}
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// Various inspectors.
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/*! @returns true if any data select line is active; @c false otherwise. */
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forceinline bool data_select_active() const {
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return bool(operation & (SelectWord | SelectByte | InterruptAcknowledge));
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}
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/*!
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@returns 0 if this byte access wants the low part of a 16-bit word; 8 if it wants the high part,
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i.e. take a word quantity and shift it right by this amount to get the quantity being
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accessed into the lowest value byte.
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*/
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forceinline unsigned int byte_shift() const {
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return ~(*address << 3) & 8;
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}
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/*!
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Obtains the mask to apply to a word that will leave only the byte this microcycle is selecting.
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@returns 0x00ff if this byte access wants the low part of a 16-bit word; 0xff00 if it wants the high part.
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*/
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forceinline uint16_t byte_mask() const {
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return uint16_t(0xff00 >> ((*address << 3) & 8));
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}
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/*!
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Obtains the mask to apply to a word that will leave only the byte this microcycle **isn't** selecting.
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i.e. this is the part of a word that should be untouched by this microcycle.
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@returns 0xff00 if this byte access wants the low part of a 16-bit word; 0x00ff if it wants the high part.
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*/
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forceinline uint16_t untouched_byte_mask() const {
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return uint16_t(0x00ff << ((*address << 3) & 8));
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}
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/*!
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Assuming this cycle is a byte write, mutates @c destination by writing the byte to the proper upper or
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lower part, retaining the other half.
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*/
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forceinline uint16_t write_byte(uint16_t destination) const {
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return uint16_t((destination & untouched_byte_mask()) | (value->b << byte_shift()));
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}
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/*!
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@returns non-zero if the 68000 LDS is asserted; zero otherwise.
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*/
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forceinline int lower_data_select() const {
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return (operation & SelectByte & *address) | (operation & SelectWord);
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}
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/*!
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@returns non-zero if the 68000 UDS is asserted; zero otherwise.
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*/
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forceinline int upper_data_select() const {
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return (operation & SelectByte & ~*address) | (operation & SelectWord);
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}
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/*!
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@returns the address being accessed at the precision a 68000 supplies it —
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only 24 address bit precision, with the low bit shifted out. So it's the
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68000 address at word precision: address 0 is the first word in the address
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space, address 1 is the second word (i.e. the third and fourth bytes) in
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the address space, etc.
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*/
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forceinline uint32_t word_address() const {
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return (address ? *address & 0x00fffffe : 0) >> 1;
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}
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/*!
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@returns the same value as word_address() for any Microcycle with the NewAddress or
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SameAddress flags set; undefined behaviour otherwise.
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*/
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forceinline uint32_t active_operation_word_address() const {
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return (*address & 0x00fffffe) >> 1;
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}
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/*!
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@returns the address of the word or byte being accessed at byte precision,
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in the endianness of the host platform.
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So: if this is a word access, and the 68000 wants to select the word at address
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@c n, this will evaluate to @c n regardless of the host machine's endianness..
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If this is a byte access and the host machine is big endian it will evalue to @c n.
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If the host machine is little endian then it will evaluate to @c n^1.
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*/
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forceinline uint32_t host_endian_byte_address() const {
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#if TARGET_RT_BIG_ENDIAN
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return *address & 0xffffff;
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#else
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return (*address ^ (operation & SelectByte)) & 0xffffff;
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#endif
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}
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/*!
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@returns the value on the data bus — all 16 bits, with any inactive lines
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(as er the upper and lower data selects) being represented by 1s. Assumes
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this is a write cycle.
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*/
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forceinline uint16_t value16() const {
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const uint16_t values[] = { value->w, uint16_t((value->b << 8) | value->b) };
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return values[operation & SelectByte];
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}
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/*!
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@returns the value currently on the high 8 lines of the data bus.
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*/
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forceinline uint8_t value8_high() const {
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const uint8_t values[] = { uint8_t(value->w >> 8), value->b};
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return values[operation & SelectByte];
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}
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/*!
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@returns the value currently on the low 8 lines of the data bus.
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*/
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forceinline uint8_t value8_low() const {
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return value->b;
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}
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/*!
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Sets to @c value the 8- or 16-bit portion of the supplied value that is
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currently being read. Assumes this is a read cycle.
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*/
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forceinline void set_value16(uint16_t v) const {
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assert(operation & Microcycle::Read);
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if(operation & Microcycle::SelectWord) {
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value->w = v;
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} else {
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value->b = uint8_t(v >> byte_shift());
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}
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}
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/*!
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Equivalent to set_value16((v << 8) | 0x00ff).
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*/
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forceinline void set_value8_high(uint8_t v) const {
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assert(operation & Microcycle::Read);
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if(operation & Microcycle::SelectWord) {
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value->w = uint16_t(0x00ff | (v << 8));
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} else {
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value->b = uint8_t(v | byte_mask());
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}
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}
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/*!
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Equivalent to set_value16(v | 0xff00).
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*/
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forceinline void set_value8_low(uint8_t v) const {
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assert(operation & Microcycle::Read);
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if(operation & Microcycle::SelectWord) {
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value->w = 0xff00 | v;
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} else {
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value->b = uint8_t(v | untouched_byte_mask());
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}
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}
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// PermitRead and PermitWrite are used as part of the read/write mask
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// supplied to @c apply; they are picked to be small enough values that
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// a byte can be used for storage.
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static constexpr OperationT PermitRead = 1 << 3;
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static constexpr OperationT PermitWrite = 1 << 4;
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/*!
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Assuming this to be a cycle with a data select active, applies it to @c target
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subject to the read_write_mask, where 'applies' means:
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* if this is a byte read, reads a single byte from @c target;
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* if this is a word read, reads a word (in the host platform's endianness) from @c target; and
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* if this is a write, does the converse of a read.
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*/
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forceinline void apply(uint8_t *target, OperationT read_write_mask = PermitRead | PermitWrite) const {
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assert( (operation & (SelectWord | SelectByte)) != (SelectWord | SelectByte));
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switch((operation | read_write_mask) & (SelectWord | SelectByte | Read | PermitRead | PermitWrite)) {
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default:
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break;
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case SelectWord | Read | PermitRead:
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case SelectWord | Read | PermitRead | PermitWrite:
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value->w = *reinterpret_cast<uint16_t *>(target);
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break;
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case SelectByte | Read | PermitRead:
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case SelectByte | Read | PermitRead | PermitWrite:
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value->b = *target;
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break;
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case SelectWord | PermitWrite:
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case SelectWord | PermitWrite | PermitRead:
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*reinterpret_cast<uint16_t *>(target) = value->w;
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break;
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case SelectByte | PermitWrite:
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case SelectByte | PermitWrite | PermitRead:
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*target = value->b;
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break;
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}
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}
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};
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/*!
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This is the prototype for a 68000 bus handler; real bus handlers can descend from this
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in order to get default implementations of any changes that may occur in the expected interface.
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*/
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class BusHandler {
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public:
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/*!
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Provides the bus handler with a single Microcycle to 'perform'.
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FC0 and FC1 are provided inside the microcycle as the IsData and IsProgram
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flags; FC2 is provided here as is_supervisor — it'll be either 0 or 1.
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*/
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HalfCycles perform_bus_operation([[maybe_unused]] const Microcycle &cycle, [[maybe_unused]] int is_supervisor) {
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return HalfCycles(0);
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}
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/*!
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Provides information about the path of execution if enabled via the template.
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*/
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void will_perform([[maybe_unused]] uint32_t address, [[maybe_unused]] uint16_t opcode) {}
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};
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struct State {
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InstructionSet::M68k::RegisterSet registers;
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};
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}
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}
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#include "Implementation/68000Mk2Storage.hpp"
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namespace CPU {
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namespace MC68000Mk2 {
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/*!
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Provides an emulation of the 68000 with accurate bus logic via the @c BusHandler, subject to the following template parameters:
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@c dtack_is_implicit means that the 68000 won't wait around for DTACK during any data access. BERR or VPA may still be
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signalled at the appropriate moment and will override the implicit DTACK, but the processor won't spin if nothing is explicitly
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signalled. Enabling this simplifies the internal state machine and therefore improves performance; bus handlers can still indicate
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that time was spent waiting for DTACK by returning an appropriate value from @c perform_bus_operation.
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@c permit_overrun allows the 68000 to be relaxed in how it interprets the constraint specified by the @c duration parameter to
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@c run_for. If this is @c false, @c run_for will always return as soon as it has called @c perform_bus_operation with whichever
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operation is ongoing at the requested stopping time. If it is @c true then the 68000 is granted leeway to overrun the requested stop
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time by 'a small amount' as and when it is a benefit to do so. Any overrun will be subtracted from the next @c run_for.
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In practice this allows the implementation to avoid a bunch of conditional checks by considering whether it needs to exit less frequently.
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Teleologically, it's expected that most — if not all — single-processor machines can permit overruns for a performance boost with
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no user-visible difference.
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@c signal_will_perform indicates whether the 68000 will call the bus handler's @c will_perform. Unlike the popular 8-bit CPUs,
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the 68000 doesn't offer an indication of when instruction dispatch will occur so this is provided *for testing purposes*. It allows test cases
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to track execution and inspect internal state in a wholly unrealistic fashion.
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*/
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template <class BusHandler, bool dtack_is_implicit = true, bool permit_overrun = true, bool signal_will_perform = false>
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class Processor: private ProcessorBase {
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public:
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Processor(BusHandler &bus_handler) : ProcessorBase(), bus_handler_(bus_handler) {}
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Processor(const Processor& rhs) = delete;
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Processor& operator=(const Processor& rhs) = delete;
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void run_for(HalfCycles duration);
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/// @returns The current processor state.
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CPU::MC68000Mk2::State get_state();
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/// Sets the current processor state.
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void set_state(const CPU::MC68000Mk2::State &);
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/// Sets all registers to the values provided, fills the prefetch queue and ensures the
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/// next action the processor will take is to decode whatever is in the queue.
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///
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/// The queue is filled synchronously, during this call, causing calls to the bus handler.
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void decode_from_state(const InstructionSet::M68k::RegisterSet &);
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// TODO: bus ack/grant, halt,
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/// Sets the DTack line — @c true for active, @c false for inactive.
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inline void set_dtack(bool dtack) {
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dtack_ = dtack;
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}
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/// Sets the VPA (valid peripheral address) line — @c true for active, @c false for inactive.
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inline void set_is_peripheral_address(bool is_peripheral_address) {
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vpa_ = is_peripheral_address;
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}
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/// Sets the bus error line — @c true for active, @c false for inactive.
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inline void set_bus_error(bool bus_error) {
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berr_ = bus_error;
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}
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/// Sets the interrupt lines, IPL0, IPL1 and IPL2.
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inline void set_interrupt_level(int interrupt_level) {
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bus_interrupt_level_ = interrupt_level;
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}
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/// @returns The current phase of the E clock; this will be a number of
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/// half-cycles between 0 and 19 inclusive, indicating how far the 68000
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/// is into the current E cycle.
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///
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/// This is guaranteed to be 0 at initial 68000 construction. It is not guaranteed
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/// to return the correct result if called during a bus transaction.
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HalfCycles get_e_clock_phase() {
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return e_clock_phase_;
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}
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void reset();
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private:
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BusHandler &bus_handler_;
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};
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}
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}
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#include "Implementation/68000Mk2Implementation.hpp"
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#endif /* _8000Mk2_h */
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