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174 lines
4.1 KiB
C++
174 lines
4.1 KiB
C++
//
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// SCSICard.cpp
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// Clock Signal
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//
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// Created by Thomas Harte on 22/08/2022.
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// Copyright © 2022 Thomas Harte. All rights reserved.
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//
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// Per the documentation around the GGLabs Apple II SCSI card clone:
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//
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// A 5380 is mapped to the first eight bytes of slot IO:
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//
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// $c0x0 R current SCSI data register
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// $c0x0 W output data register
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// $c0x1 R/W initiator command register
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// $c0x2 R/W mode select register
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// $c0x3 R/W target command register
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// $c0x4 R SCSI bus status
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// $c0x4 W select enable register
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// $c0x5 R bus and status register
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// $c0x6 R input data register
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// $c0x7 R reset parity and interrupts
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// (i.e. the 5380's standard registers in their usual order)
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//
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// The remaining eight are used for control functions:
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//
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// $c0x8 R/W PDMA/DACK
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// $c0x9 R SCSI device ID
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// $c0xa W memory bank select register
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// $c0xb W reset 5380 SCSI chip
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// $c0xc - [unused]
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// $c0xd W PDMA mode enable
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// $c0xe R read DRQ status through bit 7
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// $c0xf - [unused]
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//
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// Further, per that card's schematic:
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//
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// BANK REGISTER: bit 0..3 ROM Addr, 4..6 RAM Addr, 7 RSVD
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//
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// Which relates to the description:
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//
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// The card is also equipped with 16K of ROM and 8K of RAM.
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// These are mapped in the $C800-$CFFF card memory using a banking
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// scheme. The $C0xA bank register selects the which bank of RAM
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// and ROM are mapped. RAM is always at $C800-$CBFF and ROM is
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// at $CC00-$CFFF. The boot code in the first 256 bytes of ROM
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// bank 0 is also mapped in the IOSEL space ($Cn00-$CnFF).
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//
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#include "SCSICard.hpp"
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#include <cstring>
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using namespace Apple::II;
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ROM::Request SCSICard::rom_request() {
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return ROM::Request(ROM::Name::AppleIISCSICard);
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}
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// TODO: accept and supply real clock rate.
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SCSICard::SCSICard(ROM::Map &map, int clock_rate) :
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scsi_bus_(clock_rate),
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ncr5380_(scsi_bus_, clock_rate),
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storage_(scsi_bus_, 6)
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{
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// Grab a copy of the SCSI ROM.
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const auto rom = map.find(ROM::Name::AppleIISCSICard);
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if(rom == map.end()) {
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throw ROMMachine::Error::MissingROMs;
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}
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memcpy(rom_.data(), rom->second.data(), rom_.size());
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// Set up initial banking.
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rom_pointer_ = rom_.data();
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ram_pointer_ = ram_.data();
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}
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void SCSICard::perform_bus_operation(Select select, bool is_read, uint16_t address, uint8_t *value) {
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switch(select) {
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default: break;
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case Select::IO:
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if(is_read) {
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*value = rom_[address & 255];
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}
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break;
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case Select::Device:
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address &= 0xf;
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switch(address) {
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case 0x0: case 0x1: case 0x2: case 0x3:
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case 0x4: case 0x5: case 0x6: case 0x7:
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if(is_read) {
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*value = ncr5380_.read(address);
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} else {
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ncr5380_.write(address, *value);
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}
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break;
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case 0x9:
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if(is_read) {
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*value = uint8_t(ncr5380_.scsi_id());
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}
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break;
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case 0x8:
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// DMA acknowledge.
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if(is_read) {
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*value = ncr5380_.dma_acknowledge();
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} else {
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ncr5380_.dma_acknowledge(*value);
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}
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break;
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case 0xa:
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// RAM and ROM select.
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if(!is_read) {
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const auto rom_base = size_t((*value & 0x0f) << 10);
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const auto ram_base = size_t((*value & 0x70) << 6);
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rom_pointer_ = &rom_[rom_base];
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ram_pointer_ = &ram_[ram_base];
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}
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break;
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case 0xb:
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if(!is_read) {
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logger_.error().append("TODO: NCR reset");
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}
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break;
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case 0xd:
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if(!is_read) {
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logger_.error().append("TODO: Enable PDMA");
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}
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break;
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case 0xe:
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// DRQ in b7.
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if(is_read) {
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*value = ncr5380_.dma_request() ? 0x80 : 0x00;
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}
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break;
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default:
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logger_.error().append("Unhandled: %04x %c %02x\n", address, is_read ? 'r' : 'w', *value);
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break;
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}
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break;
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case Select::C8Region:
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if(address & 0x400) {
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if(is_read) {
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*value = rom_pointer_[address & 0x3ff];
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}
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} else {
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if(is_read) {
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*value = ram_pointer_[address & 0x3ff];
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} else {
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ram_pointer_[address & 0x3ff] = *value;
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}
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}
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break;
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}
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}
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void SCSICard::set_storage_device(const std::shared_ptr<Storage::MassStorage::MassStorageDevice> &device) {
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storage_->set_storage(device);
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}
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void SCSICard::set_activity_observer(Activity::Observer *observer) {
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scsi_bus_.set_activity_observer(observer);
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}
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