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mirror of https://github.com/TomHarte/CLK.git synced 2024-11-29 12:50:28 +00:00
CLK/Components
Thomas Harte e94b9f695a Move interrupt away from buggy position.
Since I don't know where it's supposed to go anyway.
2023-05-08 09:50:05 -04:00
..
1770
5380 Continue DMA requests if writing, even after a phase mismatch. 2022-09-15 16:46:22 -04:00
6522 Eliminate unused #includes. 2021-07-18 11:35:57 -04:00
6526 Avoid unnecessary get_port_input calls. 2021-11-24 17:15:48 -05:00
6532
6560 Switch name back to emphasise _async_. 2022-07-16 14:41:04 -04:00
6845
6850 Introduce the principle that a Serial::Line can be two-wire — clock + data. 2021-11-06 16:54:20 -07:00
8255
8272
8530
9918 Move interrupt away from buggy position. 2023-05-08 09:50:05 -04:00
68901 Fix include order. 2023-01-14 14:16:56 -05:00
AppleClock Establishes valid initial BRAM. 2021-09-10 19:56:20 -04:00
AudioToggle Switch name back to emphasise _async_. 2022-07-16 14:41:04 -04:00
AY38910 Switch name back to emphasise _async_. 2022-07-16 14:41:04 -04:00
DiskII Walk back slightly. 2021-10-14 18:02:58 -07:00
KonamiSCC Switch name back to emphasise _async_. 2022-07-16 14:41:04 -04:00
OPx Switch name back to emphasise _async_. 2022-07-16 14:41:04 -04:00
RP5C01 Months seem to start at 1; also fix seeded year for MSX. 2023-01-23 22:52:26 -05:00
Serial Add header for assert. 2021-11-24 16:28:18 -05:00
SN76489 Switch name back to emphasise _async_. 2022-07-16 14:41:04 -04:00