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123 lines
2.8 KiB
C++
123 lines
2.8 KiB
C++
//
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// Z80AllRAM.cpp
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// Clock Signal
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//
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// Created by Thomas Harte on 16/05/2017.
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// Copyright 2017 Thomas Harte. All rights reserved.
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//
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#include "Z80AllRAM.hpp"
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#include <algorithm>
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using namespace CPU::Z80;
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namespace {
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class ConcreteAllRAMProcessor: public AllRAMProcessor, public BusHandler {
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public:
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ConcreteAllRAMProcessor() : AllRAMProcessor(), z80_(*this) {}
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inline HalfCycles perform_machine_cycle(const PartialMachineCycle &cycle) {
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timestamp_ += cycle.length;
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if(!cycle.is_terminal()) {
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return HalfCycles(0);
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}
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uint16_t address = cycle.address ? *cycle.address : 0x0000;
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switch(cycle.operation) {
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case PartialMachineCycle::ReadOpcode:
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check_address_for_trap(address);
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case PartialMachineCycle::Read:
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*cycle.value = memory_[address];
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break;
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case PartialMachineCycle::Write:
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memory_[address] = *cycle.value;
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break;
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case PartialMachineCycle::Output:
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break;
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case PartialMachineCycle::Input:
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*cycle.value = port_delegate_ ? port_delegate_->z80_all_ram_processor_input(address) : 0xff;
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break;
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case PartialMachineCycle::Internal:
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case PartialMachineCycle::Refresh:
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break;
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case PartialMachineCycle::Interrupt:
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// A pick that means LD HL, (nn) if interpreted as an instruction but is otherwise
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// arbitrary.
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*cycle.value = 0x21;
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break;
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default:
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break;
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}
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if(memory_delegate_ != nullptr) {
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memory_delegate_->z80_all_ram_processor_did_perform_bus_operation(*this, cycle.operation, address, cycle.value ? *cycle.value : 0x00, timestamp_);
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}
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return HalfCycles(0);
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}
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void run_for(const Cycles cycles) final {
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z80_.run_for(cycles);
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}
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void run_for_instruction() final {
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int toggles = 0;
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int cycles = 0;
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// Run:
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// (1) until is_starting_new_instruction is true;
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// (2) until it is false again; and
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// (3) until it is true again.
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while(true) {
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if(z80_.is_starting_new_instruction() != (toggles&1)) {
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++toggles;
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if(toggles == 3) break;
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}
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z80_.run_for(Cycles(1));
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++cycles;
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}
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}
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uint16_t get_value_of_register(Register r) final {
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return z80_.get_value_of_register(r);
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}
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void set_value_of_register(Register r, uint16_t value) final {
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z80_.set_value_of_register(r, value);
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}
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bool get_halt_line() final {
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return z80_.get_halt_line();
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}
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void reset_power_on() final {
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return z80_.reset_power_on();
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}
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void set_interrupt_line(bool value) final {
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z80_.set_interrupt_line(value);
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}
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void set_non_maskable_interrupt_line(bool value) final {
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z80_.set_non_maskable_interrupt_line(value);
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}
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void set_wait_line(bool value) final {
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z80_.set_wait_line(value);
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}
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private:
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CPU::Z80::Processor<ConcreteAllRAMProcessor, false, true> z80_;
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bool was_m1_ = false;
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};
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}
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AllRAMProcessor *AllRAMProcessor::Processor() {
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return new ConcreteAllRAMProcessor;
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}
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