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763 lines
23 KiB
C++
763 lines
23 KiB
C++
//
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//
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// ExecutorImplementation.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 01/05/2022.
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// Copyright © 2022 Thomas Harte. All rights reserved.
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//
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#pragma once
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#include "../Perform.hpp"
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#include "../ExceptionVectors.hpp"
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#include <cassert>
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namespace InstructionSet::M68k {
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#define An(x) state_.registers[8 + x]
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#define Dn(x) state_.registers[x]
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#define sp An(7)
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#define AccessException(code, address, vector) \
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uint64_t(((vector) << 8) | uint64_t(code) | ((address) << 16))
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// MARK: - Executor itself.
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template <Model model, typename BusHandler>
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Executor<model, BusHandler>::Executor(BusHandler &handler) : state_(handler) {
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reset();
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}
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template <Model model, typename BusHandler>
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void Executor<model, BusHandler>::reset() {
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// Establish: supervisor state, all interrupts blocked.
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state_.status.set_status(0b0010'0011'1000'0000);
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state_.did_update_status();
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// Clear the STOPped state, if currently active.
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state_.stopped = false;
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// Seed stack pointer and program counter.
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sp.l = state_.template read<uint32_t>(0) & 0xffff'fffe;
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state_.program_counter.l = state_.template read<uint32_t>(4);
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}
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template <Model model, typename BusHandler>
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void Executor<model, BusHandler>::signal_bus_error(const FunctionCode code, const uint32_t address) {
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throw AccessException(code, address, Exception::AccessFault);
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}
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template <Model model, typename BusHandler>
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void Executor<model, BusHandler>::set_interrupt_level(const int level) {
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state_.interrupt_input_ = level;
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state_.stopped &= !state_.status.would_accept_interrupt(level);
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}
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template <Model model, typename BusHandler>
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void Executor<model, BusHandler>::run_for_instructions(int count) {
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if(state_.stopped) return;
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while(count > 0) {
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try {
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state_.run(count);
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} catch (uint64_t exception) {
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// Potiental source of an exception #1: STOP. Check for that first.
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if(state_.stopped) return;
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// Unpack the exception; this is the converse of the AccessException macro.
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const int vector_address = (exception >> 6) & 0xfc;
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const uint16_t code = uint16_t(exception & 0xff);
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const uint32_t faulting_address = uint32_t(exception >> 16);
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// Grab the status to store, then switch into supervisor mode.
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const uint16_t status = state_.status.status();
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state_.status.is_supervisor = true;
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state_.status.trace_flag = 0;
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state_.did_update_status();
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// Ensure no tracing occurs into the exception.
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state_.should_trace = 0;
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// Push status and the program counter at instruction start.
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state_.template write<uint16_t>(sp.l - 14, code);
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state_.template write<uint32_t>(sp.l - 12, faulting_address);
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state_.template write<uint16_t>(sp.l - 8, state_.instruction_opcode);
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state_.template write<uint16_t>(sp.l - 6, status);
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state_.template write<uint16_t>(sp.l - 4, state_.instruction_address);
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sp.l -= 14;
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// Fetch the new program counter; reset on a double fault.
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try {
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state_.program_counter.l = state_.template read<uint32_t>(vector_address);
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} catch (uint64_t) {
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// TODO: I think this is incorrect, but need to verify consistency
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// across different 680x0s.
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reset();
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}
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}
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}
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}
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template <Model model, typename BusHandler>
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RegisterSet Executor<model, BusHandler>::get_state() const {
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RegisterSet result;
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for(int c = 0; c < 8; c++) {
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result.data[c] = Dn(c).l;
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}
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for(int c = 0; c < 7; c++) {
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result.address[c] = An(c).l;
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}
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result.status = state_.status.status();
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result.program_counter = state_.program_counter.l;
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state_.stack_pointers[state_.active_stack_pointer] = sp;
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result.user_stack_pointer = state_.stack_pointers[0].l;
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result.supervisor_stack_pointer = state_.stack_pointers[1].l;
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return result;
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}
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template <Model model, typename BusHandler>
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void Executor<model, BusHandler>::set_state(const RegisterSet &state) {
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for(int c = 0; c < 8; c++) {
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Dn(c).l = state.data[c];
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}
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for(int c = 0; c < 7; c++) {
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An(c).l = state.address[c];
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}
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state_.status.set_status(state.status);
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state_.did_update_status();
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state_.program_counter.l = state.program_counter;
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state_.stack_pointers[0].l = state.user_stack_pointer;
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state_.stack_pointers[1].l = state.supervisor_stack_pointer;
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sp = state_.stack_pointers[state_.active_stack_pointer];
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}
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#undef Dn
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#undef An
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// MARK: - State.
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#define An(x) registers[8 + x]
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#define Dn(x) registers[x]
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template <Model model, typename BusHandler>
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template <typename IntT>
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IntT Executor<model, BusHandler>::State::read(const uint32_t address, const bool is_from_pc) {
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const auto code = FunctionCode((active_stack_pointer << 2) | 1 << int(is_from_pc));
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if(model == Model::M68000 && sizeof(IntT) > 1 && address & 1) {
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throw AccessException(code, address, Exception::AddressError | (int(is_from_pc) << 3) | (1 << 4));
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}
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return bus_handler_.template read<IntT>(address, code);
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}
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template <Model model, typename BusHandler>
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template <typename IntT>
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void Executor<model, BusHandler>::State::write(const uint32_t address, const IntT value) {
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const auto code = FunctionCode((active_stack_pointer << 2) | 1);
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if(model == Model::M68000 && sizeof(IntT) > 1 && address & 1) {
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throw AccessException(code, address, Exception::AddressError);
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}
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bus_handler_.template write<IntT>(address, value, code);
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}
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template <Model model, typename BusHandler>
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void Executor<model, BusHandler>::State::read(const DataSize size, const uint32_t address, CPU::SlicedInt32 &value) {
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switch(size) {
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case DataSize::Byte: value.b = read<uint8_t>(address); break;
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case DataSize::Word: value.w = read<uint16_t>(address); break;
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case DataSize::LongWord: value.l = read<uint32_t>(address); break;
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}
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}
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template <Model model, typename BusHandler>
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void Executor<model, BusHandler>::State::write(const DataSize size, const uint32_t address, CPU::SlicedInt32 value) {
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switch(size) {
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case DataSize::Byte: write<uint8_t>(address, value.b); break;
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case DataSize::Word: write<uint16_t>(address, value.w); break;
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case DataSize::LongWord: write<uint32_t>(address, value.l); break;
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}
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}
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template <Model model, typename BusHandler>
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template <typename IntT> IntT Executor<model, BusHandler>::State::read_pc() {
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const IntT result = read<IntT>(program_counter.l, true);
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if constexpr (sizeof(IntT) == 4) {
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program_counter.l += 4;
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} else {
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program_counter.l += 2;
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}
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return result;
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}
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// For all of below, cf PRM 2-2 (PDF p43)
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template <Model model, typename BusHandler>
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uint32_t Executor<model, BusHandler>::State::index_8bitdisplacement(uint32_t base) {
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// Determine whether full extension addressing modes are supported.
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constexpr bool supports_full_extensions = model >= Model::M68020;
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// Get the [first] extension word.
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const auto extension = read_pc<uint16_t>();
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// The 68000, 68080 and 68010 do not support the scale field, and are limited
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// to brief extension words.
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const int scale = supports_full_extensions ? (extension >> 9) & 3 : 0;
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// Decode brief instruction word fields.
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const auto offset = int8_t(extension);
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const int register_index = (extension >> 12) & 15;
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// Calculate the displacement; which on the 68020+ is better known as the index.
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const uint32_t raw_index = registers[register_index].l;
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uint32_t index = ((extension & 0x800) ? raw_index : int16_t(raw_index)) << scale;
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// Use a brief extension word if instructed to, or if that's this processor's limit.
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if(!supports_full_extensions || !(extension & 0x100)) {
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return base + offset + index;
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}
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//
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// Determine a long extension.
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//
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// Apply suppressions.
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const bool suppress_base = extension & 0x80; // i.e. don't use whatever the first instruction word indicated.
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const bool suppress_index = extension & 0x40; // i.e. don't use whatever register_index points to.
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if(suppress_base) base = 0;
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if(suppress_index) index = 0;
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// Fetch base displacement.
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uint32_t base_displacement = 0;
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switch((extension >> 4) & 3) {
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default: break;
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case 2: base_displacement = read_pc<uint16_t>(); break;
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case 3: base_displacement = read_pc<uint32_t>(); break;
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}
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// Don't do a further indirection if there's no outer displacement.
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if(!(extension & 7)) {
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return index + base + base_displacement;
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}
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// Fetch outer displacement.
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uint32_t outer_displacement = 0;
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switch(extension & 3) {
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default: break;
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case 2: outer_displacement = read_pc<uint16_t>(); break;
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case 3: outer_displacement = read_pc<uint32_t>(); break;
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}
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// Apply outer displacement; either the index is before the indirection
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// or after it.
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if(extension & 4) {
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return read<uint32_t>(base + base_displacement) + index + outer_displacement;
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} else {
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return read<uint32_t>(base + base_displacement + index) + outer_displacement;
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}
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}
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template <Model model, typename BusHandler>
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typename Executor<model, BusHandler>::State::EffectiveAddress
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Executor<model, BusHandler>::State::calculate_effective_address(
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const Preinstruction instruction,
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const uint16_t opcode,
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const int index
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) {
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EffectiveAddress ea;
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switch(instruction.mode(index)) {
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case AddressingMode::None:
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// Permit an uninitialised effective address to be returned;
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// this value shouldn't be used.
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break;
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//
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// Operands that don't have effective addresses, which are returned as values.
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//
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case AddressingMode::DataRegisterDirect:
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case AddressingMode::AddressRegisterDirect:
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ea.value = registers[instruction.lreg(index)];
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ea.requires_fetch = false;
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break;
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case AddressingMode::Quick:
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ea.value.l = quick(opcode, instruction.operation);
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ea.requires_fetch = false;
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break;
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case AddressingMode::ImmediateData:
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switch(instruction.operand_size()) {
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case DataSize::Byte:
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ea.value.l = read_pc<uint16_t>() & 0xff;
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break;
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case DataSize::Word:
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ea.value.l = read_pc<uint16_t>();
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break;
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case DataSize::LongWord:
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ea.value.l = read_pc<uint32_t>();
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break;
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}
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ea.requires_fetch = false;
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break;
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case AddressingMode::ExtensionWord:
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ea.value.l = read_pc<uint16_t>();
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ea.requires_fetch = false;
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break;
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//
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// Absolute addresses.
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//
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case AddressingMode::AbsoluteShort:
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ea.value.l = int16_t(read_pc<uint16_t>());
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ea.requires_fetch = true;
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break;
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case AddressingMode::AbsoluteLong:
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ea.value.l = read_pc<uint32_t>();
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ea.requires_fetch = true;
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break;
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//
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// Address register indirects.
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//
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case AddressingMode::AddressRegisterIndirect:
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ea.value = An(instruction.reg(index));
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ea.requires_fetch = true;
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break;
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case AddressingMode::AddressRegisterIndirectWithPostincrement: {
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const auto reg = instruction.reg(index);
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ea.value = An(reg);
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ea.requires_fetch = true;
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switch(instruction.operand_size()) {
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case DataSize::Byte: An(reg).l += byte_increments[reg]; break;
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case DataSize::Word: An(reg).l += 2; break;
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case DataSize::LongWord: An(reg).l += 4; break;
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}
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} break;
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case AddressingMode::AddressRegisterIndirectWithPredecrement: {
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const auto reg = instruction.reg(index);
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switch(instruction.operand_size()) {
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case DataSize::Byte: An(reg).l -= byte_increments[reg]; break;
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case DataSize::Word: An(reg).l -= 2; break;
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case DataSize::LongWord: An(reg).l -= 4; break;
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}
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ea.value = An(reg);
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ea.requires_fetch = true;
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} break;
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case AddressingMode::AddressRegisterIndirectWithDisplacement:
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ea.value.l = An(instruction.reg(index)).l + int16_t(read_pc<uint16_t>());
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ea.requires_fetch = true;
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break;
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case AddressingMode::AddressRegisterIndirectWithIndex8bitDisplacement:
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ea.value.l = index_8bitdisplacement(An(instruction.reg(index)).l);
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ea.requires_fetch = true;
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break;
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//
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// PC-relative addresses.
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//
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case AddressingMode::ProgramCounterIndirectWithDisplacement:
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ea.value.l = program_counter.l;
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ea.value.l += int16_t(read_pc<uint16_t>());
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ea.requires_fetch = true;
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break;
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case AddressingMode::ProgramCounterIndirectWithIndex8bitDisplacement:
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ea.value.l = index_8bitdisplacement(program_counter.l);
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ea.requires_fetch = true;
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break;
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default:
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assert(false);
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}
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return ea;
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}
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template <Model model, typename BusHandler>
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void Executor<model, BusHandler>::State::run(int &count) {
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while(count--) {
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// Check for a new interrupt.
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if(status.would_accept_interrupt(interrupt_input)) {
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const int vector = bus_handler_.acknowlege_interrupt(interrupt_input);
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if(vector >= 0) {
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raise_exception<false>(vector);
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} else {
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raise_exception<false>(Exception::InterruptAutovectorBase - 1 + interrupt_input);
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}
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status.interrupt_level = interrupt_input;
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}
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// Capture the trace bit, indicating whether to trace
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// after this instruction.
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//
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// If an exception occurs, this value will be cleared, but
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// it'll persist across mere status register changes for
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// one instruction's duration.
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should_trace = status.trace_flag;
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// Read the next instruction.
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instruction_address = program_counter.l;
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instruction_opcode = read_pc<uint16_t>();
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const Preinstruction instruction = decoder_.decode(instruction_opcode);
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if(instruction.requires_supervisor() && !status.is_supervisor) {
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raise_exception(Exception::PrivilegeViolation);
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continue;
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}
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if(instruction.operation == Operation::Undefined) {
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switch(instruction_opcode & 0xf000) {
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default:
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raise_exception(Exception::IllegalInstruction);
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continue;
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case 0xa000:
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raise_exception(Exception::Line1010);
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continue;
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case 0xf000:
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raise_exception(Exception::Line1111);
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continue;
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}
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}
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// Temporary storage.
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CPU::SlicedInt32 operand_[2];
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EffectiveAddress effective_address_[2];
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// Calculate effective addresses; copy 'addresses' into the
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// operands by default both: (i) because they might be values,
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// rather than addresses; and (ii) then they'll be there for use
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// by LEA and PEA.
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effective_address_[0] = calculate_effective_address(instruction, instruction_opcode, 0);
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effective_address_[1] = calculate_effective_address(instruction, instruction_opcode, 1);
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operand_[0] = effective_address_[0].value;
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operand_[1] = effective_address_[1].value;
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// Obtain the appropriate sequence.
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const auto flags = operand_flags<model>(instruction.operation);
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#define fetch_operand(n) \
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if(effective_address_[n].requires_fetch) { \
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read(instruction.operand_size(), effective_address_[n].value.l, operand_[n]); \
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}
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if(flags & FetchOp1) { fetch_operand(0); }
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if(flags & FetchOp2) { fetch_operand(1); }
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#undef fetch_operand
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perform<model>(instruction, operand_[0], operand_[1], status, *this);
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#define store_operand(n) \
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if(!effective_address_[n].requires_fetch) { \
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registers[instruction.lreg(n)] = operand_[n]; \
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} else { \
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write(instruction.operand_size(), effective_address_[n].value.l, operand_[n]); \
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}
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if(flags & StoreOp1) { store_operand(0); }
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if(flags & StoreOp2) { store_operand(1); }
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#undef store_operand
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// If the trace bit was set, trigger the trace exception.
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if(should_trace) {
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raise_exception<false>(Exception::Trace);
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}
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}
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}
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// MARK: - Flow Control.
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template <Model model, typename BusHandler>
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template <bool use_current_instruction_pc>
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void Executor<model, BusHandler>::State::raise_exception(const int index) {
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const uint32_t address = index << 2;
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// Grab the status to store, then switch into supervisor mode
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// and disable tracing.
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const uint16_t previous_status = status.status();
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status.is_supervisor = true;
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status.trace_flag = 0;
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did_update_status();
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// Push status and the program counter at instruction start.
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write<uint32_t>(sp.l - 4, use_current_instruction_pc ? instruction_address : program_counter.l);
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write<uint16_t>(sp.l - 6, previous_status);
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sp.l -= 6;
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// Ensure no tracing occurs into the exception.
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should_trace = 0;
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// Fetch the new program counter.
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program_counter.l = read<uint32_t>(address);
|
|
}
|
|
|
|
template <Model model, typename BusHandler>
|
|
void Executor<model, BusHandler>::State::did_update_status() {
|
|
// Shuffle the stack pointers.
|
|
stack_pointers[active_stack_pointer] = sp;
|
|
sp = stack_pointers[int(status.is_supervisor)];
|
|
active_stack_pointer = int(status.is_supervisor);
|
|
}
|
|
|
|
template <Model model, typename BusHandler>
|
|
void Executor<model, BusHandler>::State::stop() {
|
|
stopped = true;
|
|
|
|
// Raise an exception to exit the run loop; it doesn't matter
|
|
// what value is used as long as it is a uint64_t, so 0 will do.
|
|
throw uint64_t();
|
|
}
|
|
|
|
template <Model model, typename BusHandler>
|
|
void Executor<model, BusHandler>::State::reset() {
|
|
bus_handler_.reset();
|
|
}
|
|
|
|
template <Model model, typename BusHandler>
|
|
void Executor<model, BusHandler>::State::jmp(const uint32_t address) {
|
|
program_counter.l = address;
|
|
}
|
|
|
|
template <Model model, typename BusHandler>
|
|
template <typename IntT> void Executor<model, BusHandler>::State::complete_bcc(const bool branch, const IntT offset) {
|
|
if(branch) {
|
|
program_counter.l = instruction_address + offset + 2;
|
|
}
|
|
}
|
|
|
|
template <Model model, typename BusHandler>
|
|
void Executor<model, BusHandler>::State::complete_dbcc(
|
|
const bool matched_condition,
|
|
const bool overflowed,
|
|
const int16_t offset
|
|
) {
|
|
if(!matched_condition && !overflowed) {
|
|
program_counter.l = instruction_address + offset + 2;
|
|
}
|
|
}
|
|
|
|
template <Model model, typename BusHandler>
|
|
void Executor<model, BusHandler>::State::bsr(const uint32_t offset) {
|
|
sp.l -= 4;
|
|
write<uint32_t>(sp.l, program_counter.l);
|
|
program_counter.l = instruction_address + offset + 2;
|
|
}
|
|
|
|
template <Model model, typename BusHandler>
|
|
void Executor<model, BusHandler>::State::jsr(const uint32_t address) {
|
|
sp.l -= 4;
|
|
write<uint32_t>(sp.l, program_counter.l);
|
|
program_counter.l = address;
|
|
}
|
|
|
|
template <Model model, typename BusHandler>
|
|
void Executor<model, BusHandler>::State::link(const Preinstruction instruction, const uint32_t offset) {
|
|
const auto reg = 8 + instruction.reg<0>();
|
|
|
|
sp.l -= 4;
|
|
write<uint32_t>(sp.l, Dn(reg).l);
|
|
Dn(reg) = sp;
|
|
sp.l += offset;
|
|
}
|
|
|
|
template <Model model, typename BusHandler>
|
|
void Executor<model, BusHandler>::State::unlink(uint32_t &address) {
|
|
sp.l = address;
|
|
address = read<uint32_t>(sp.l);
|
|
sp.l += 4;
|
|
}
|
|
|
|
template <Model model, typename BusHandler>
|
|
void Executor<model, BusHandler>::State::pea(const uint32_t address) {
|
|
sp.l -= 4;
|
|
write<uint32_t>(sp.l, address);
|
|
}
|
|
|
|
template <Model model, typename BusHandler>
|
|
void Executor<model, BusHandler>::State::rtr() {
|
|
status.set_ccr(read<uint16_t>(sp.l));
|
|
sp.l += 2;
|
|
rts();
|
|
}
|
|
|
|
template <Model model, typename BusHandler>
|
|
void Executor<model, BusHandler>::State::rte() {
|
|
status.set_status(read<uint16_t>(sp.l));
|
|
sp.l += 2;
|
|
rts();
|
|
}
|
|
|
|
template <Model model, typename BusHandler>
|
|
void Executor<model, BusHandler>::State::rts() {
|
|
program_counter.l = read<uint32_t>(sp.l);
|
|
sp.l += 4;
|
|
}
|
|
|
|
template <Model model, typename BusHandler>
|
|
void Executor<model, BusHandler>::State::tas(const Preinstruction instruction, const uint32_t address) {
|
|
uint8_t value;
|
|
if(instruction.mode<0>() != AddressingMode::DataRegisterDirect) {
|
|
value = read<uint8_t>(address);
|
|
write<uint8_t>(address, value | 0x80);
|
|
} else {
|
|
value = uint8_t(address);
|
|
Dn(instruction.reg<0>()).b = uint8_t(address | 0x80);
|
|
}
|
|
|
|
status.overflow_flag = status.carry_flag = 0;
|
|
status.zero_result = value;
|
|
status.negative_flag = value & 0x80;
|
|
}
|
|
|
|
template <Model model, typename BusHandler>
|
|
void Executor<model, BusHandler>::State::move_to_usp(const uint32_t address) {
|
|
stack_pointers[0].l = address;
|
|
}
|
|
|
|
template <Model model, typename BusHandler>
|
|
void Executor<model, BusHandler>::State::move_from_usp(uint32_t &address) {
|
|
address = stack_pointers[0].l;
|
|
}
|
|
|
|
template <Model model, typename BusHandler>
|
|
template <typename IntT>
|
|
void Executor<model, BusHandler>::State::movep(
|
|
const Preinstruction instruction,
|
|
const uint32_t source,
|
|
const uint32_t dest
|
|
) {
|
|
if(instruction.mode<0>() == AddressingMode::DataRegisterDirect) {
|
|
// Move register to memory.
|
|
const uint32_t reg = source;
|
|
uint32_t address = dest;
|
|
|
|
if constexpr (sizeof(IntT) == 4) {
|
|
write<uint8_t>(address, uint8_t(reg >> 24));
|
|
address += 2;
|
|
|
|
write<uint8_t>(address, uint8_t(reg >> 16));
|
|
address += 2;
|
|
}
|
|
|
|
write<uint8_t>(address, uint8_t(reg >> 8));
|
|
address += 2;
|
|
|
|
write<uint8_t>(address, uint8_t(reg));
|
|
} else {
|
|
// Move memory to register.
|
|
uint32_t ® = Dn(instruction.reg<1>()).l;
|
|
uint32_t address = source;
|
|
|
|
if constexpr (sizeof(IntT) == 4) {
|
|
reg = read<uint8_t>(address) << 24;
|
|
address += 2;
|
|
|
|
reg |= read<uint8_t>(address) << 16;
|
|
address += 2;
|
|
} else {
|
|
reg &= 0xffff0000;
|
|
}
|
|
|
|
reg |= read<uint8_t>(address) << 8;
|
|
address += 2;
|
|
|
|
reg |= read<uint8_t>(address);
|
|
}
|
|
}
|
|
|
|
template <Model model, typename BusHandler>
|
|
template <typename IntT>
|
|
void Executor<model, BusHandler>::State::movem_toM(const Preinstruction instruction, uint32_t source, uint32_t dest) {
|
|
// Move registers to memory. This is the only permitted use of the predecrement mode,
|
|
// which reverses output order.
|
|
|
|
if(instruction.mode<1>() == AddressingMode::AddressRegisterIndirectWithPredecrement) {
|
|
// The structure of the code in the mainline part of the executor is such
|
|
// that the address register will already have been predecremented before
|
|
// reaching here, and it'll have been by two bytes per the operand size
|
|
// rather than according to the instruction size. That's not wanted, so undo it.
|
|
//
|
|
// TODO: with the caveat that the 68020+ have different behaviour:
|
|
//
|
|
// "For the MC68020, MC68030, MC68040, and CPU32, if the addressing register is also
|
|
// moved to memory, the value written is the initial register value decremented by the
|
|
// size of the operation. The MC68000 and MC68010 write the initial register value
|
|
// (not decremented)."
|
|
An(instruction.reg<1>()).l += 2;
|
|
|
|
uint32_t address = An(instruction.reg<1>()).l;
|
|
int index = 15;
|
|
|
|
while(source) {
|
|
if(source & 1) {
|
|
address -= sizeof(IntT);
|
|
write<IntT>(address, IntT(registers[index].l));
|
|
}
|
|
--index;
|
|
source >>= 1;
|
|
}
|
|
|
|
An(instruction.reg<1>()).l = address;
|
|
return;
|
|
}
|
|
|
|
int index = 0;
|
|
while(source) {
|
|
if(source & 1) {
|
|
write<IntT>(dest, IntT(registers[index].l));
|
|
dest += sizeof(IntT);
|
|
}
|
|
++index;
|
|
source >>= 1;
|
|
}
|
|
}
|
|
|
|
template <Model model, typename BusHandler>
|
|
template <typename IntT>
|
|
void Executor<model, BusHandler>::State::movem_toR(const Preinstruction instruction, uint32_t source, uint32_t dest) {
|
|
// Move memory to registers.
|
|
//
|
|
// A 68000 convention has been broken here; the instruction form is:
|
|
// MOVEM <ea>, #
|
|
// ... but the instruction is encoded as [MOVEM] [#] [ea].
|
|
//
|
|
// This project's decoder decodes as #, <ea>.
|
|
int index = 0;
|
|
while(source) {
|
|
if(source & 1) {
|
|
if constexpr (sizeof(IntT) == 2) {
|
|
registers[index].l = int16_t(read<uint16_t>(dest));
|
|
} else {
|
|
registers[index].l = read<uint32_t>(dest);
|
|
}
|
|
dest += sizeof(IntT);
|
|
}
|
|
++index;
|
|
source >>= 1;
|
|
}
|
|
|
|
if(instruction.mode<1>() == AddressingMode::AddressRegisterIndirectWithPostincrement) {
|
|
// "If the effective address is specified by the postincrement mode ...
|
|
// [i]f the addressing register is also loaded from memory, the memory value is
|
|
// ignored and the register is written with the postincremented effective address."
|
|
|
|
An(instruction.reg<1>()).l = dest;
|
|
}
|
|
}
|
|
|
|
#undef sp
|
|
#undef Dn
|
|
#undef An
|
|
#undef AccessException
|
|
|
|
}
|