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223 lines
8.0 KiB
C++
223 lines
8.0 KiB
C++
//
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// State.cpp
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// Clock Signal
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//
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// Created by Thomas Harte on 13/05/2020.
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// Copyright © 2020 Thomas Harte. All rights reserved.
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//
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#include "State.hpp"
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#include <cassert>
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using namespace CPU::Z80;
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State::State(const ProcessorBase &src): State() {
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// Registers.
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registers.a = src.a_;
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registers.flags = src.get_flags();
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registers.bc = src.bc_.full;
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registers.de = src.de_.full;
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registers.hl = src.hl_.full;
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registers.bcDash = src.bcDash_.full;
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registers.deDash = src.deDash_.full;
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registers.hlDash = src.hlDash_.full;
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registers.ix = src.ix_.full;
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registers.iy = src.iy_.full;
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registers.ir = src.ir_.full;
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registers.program_counter = src.pc_.full;
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registers.stack_pointer = src.sp_.full;
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registers.memptr = src.memptr_.full;
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registers.interrupt_mode = src.interrupt_mode_;
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registers.iff1 = src.iff1_;
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registers.iff2 = src.iff2_;
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// Inputs.
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inputs.irq = src.irq_line_;
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inputs.nmi = src.nmi_line_;
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inputs.wait = src.wait_line_;
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inputs.bus_request = src.bus_request_line_;
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// Execution State.
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execution_state.is_halted = src.halt_mask_ == 0x00;
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execution_state.requests = src.request_status_;
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execution_state.last_requests = src.last_request_status_;
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execution_state.temp8 = src.temp8_;
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execution_state.temp16 = src.temp16_.full;
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execution_state.operation = src.operation_;
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execution_state.flag_adjustment_history = src.flag_adjustment_history_;
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execution_state.pc_increment = src.pc_increment_;
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execution_state.refresh_address = src.refresh_addr_.full;
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execution_state.half_cycles_into_step = src.number_of_cycles_.as<int>();
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// Search for the current holder of the scheduled_program_counter_.
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#define ContainedBy(x) (src.scheduled_program_counter_ >= &src.x[0]) && (src.scheduled_program_counter_ < &src.x[src.x.size()])
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#define Populate(x, y) \
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execution_state.phase = ExecutionState::Phase::x; \
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execution_state.steps_into_phase = int(src.scheduled_program_counter_ - &src.y[0]);
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if(ContainedBy(conditional_call_untaken_program_)) {
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Populate(UntakenConditionalCall, conditional_call_untaken_program_);
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} else if(ContainedBy(reset_program_)) {
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Populate(Reset, reset_program_);
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} else if(ContainedBy(irq_program_[0])) {
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Populate(IRQMode0, irq_program_[0]);
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} else if(ContainedBy(irq_program_[1])) {
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Populate(IRQMode1, irq_program_[1]);
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} else if(ContainedBy(irq_program_[2])) {
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Populate(IRQMode2, irq_program_[2]);
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} else if(ContainedBy(nmi_program_)) {
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Populate(NMI, nmi_program_);
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} else {
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if(src.current_instruction_page_ == &src.base_page_) {
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execution_state.instruction_page = 0;
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} else if(src.current_instruction_page_ == &src.ed_page_) {
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execution_state.instruction_page = 0xed;
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} else if(src.current_instruction_page_ == &src.fd_page_) {
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execution_state.instruction_page = 0xfd;
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} else if(src.current_instruction_page_ == &src.dd_page_) {
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execution_state.instruction_page = 0xdd;
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} else if(src.current_instruction_page_ == &src.cb_page_) {
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execution_state.instruction_page = 0xcb;
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} else if(src.current_instruction_page_ == &src.fdcb_page_) {
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execution_state.instruction_page = 0xfdcb;
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} else if(src.current_instruction_page_ == &src.ddcb_page_) {
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execution_state.instruction_page = 0xddcb;
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}
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if(ContainedBy(current_instruction_page_->fetch_decode_execute)) {
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Populate(FetchDecode, current_instruction_page_->fetch_decode_execute);
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} else {
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// There's no need to determine which opcode because that knowledge is already
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// contained in the dedicated opcode field.
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Populate(Operation, current_instruction_page_->instructions[src.operation_ & src.halt_mask_]);
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}
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}
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assert(execution_state.steps_into_phase >= 0);
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#undef Populate
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#undef ContainedBy
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}
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void State::apply(ProcessorBase &target) {
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// Registers.
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target.a_ = registers.a;
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target.set_flags(registers.flags);
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target.bc_.full = registers.bc;
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target.de_.full = registers.de;
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target.hl_.full = registers.hl;
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target.bcDash_.full = registers.bcDash;
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target.deDash_.full = registers.deDash;
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target.hlDash_.full = registers.hlDash;
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target.ix_.full = registers.ix;
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target.iy_.full = registers.iy;
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target.ir_.full = registers.ir;
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target.pc_.full = registers.program_counter;
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target.sp_.full = registers.stack_pointer;
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target.memptr_.full = registers.memptr;
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target.interrupt_mode_ = registers.interrupt_mode;
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target.iff1_ = registers.iff1;
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target.iff2_ = registers.iff2;
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// Inputs.
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target.irq_line_ = inputs.irq;
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target.nmi_line_ = inputs.nmi;
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target.wait_line_ = inputs.wait;
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target.bus_request_line_ = inputs.bus_request;
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// Execution State.
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target.halt_mask_ = execution_state.is_halted ? 0x00 : 0xff;
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target.request_status_ = execution_state.requests;
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target.last_request_status_ = execution_state.last_requests;
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target.temp8_ = execution_state.temp8;
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target.temp16_.full = execution_state.temp16;
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target.operation_ = execution_state.operation;
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target.flag_adjustment_history_ = execution_state.flag_adjustment_history;
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target.pc_increment_ = execution_state.pc_increment;
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target.refresh_addr_.full = execution_state.refresh_address;
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target.number_of_cycles_ = HalfCycles(execution_state.half_cycles_into_step);
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switch(execution_state.instruction_page) {
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default: target.current_instruction_page_ = &target.base_page_; break;
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case 0xed: target.current_instruction_page_ = &target.ed_page_; break;
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case 0xdd: target.current_instruction_page_ = &target.dd_page_; break;
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case 0xcb: target.current_instruction_page_ = &target.cb_page_; break;
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case 0xfd: target.current_instruction_page_ = &target.fd_page_; break;
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case 0xfdcb: target.current_instruction_page_ = &target.fdcb_page_; break;
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case 0xddcb: target.current_instruction_page_ = &target.ddcb_page_; break;
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}
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switch(execution_state.phase) {
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case ExecutionState::Phase::UntakenConditionalCall: target.scheduled_program_counter_ = &target.conditional_call_untaken_program_[0]; break;
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case ExecutionState::Phase::Reset: target.scheduled_program_counter_ = &target.reset_program_[0]; break;
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case ExecutionState::Phase::IRQMode0: target.scheduled_program_counter_ = &target.irq_program_[0][0]; break;
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case ExecutionState::Phase::IRQMode1: target.scheduled_program_counter_ = &target.irq_program_[1][0]; break;
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case ExecutionState::Phase::IRQMode2: target.scheduled_program_counter_ = &target.irq_program_[2][0]; break;
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case ExecutionState::Phase::NMI: target.scheduled_program_counter_ = &target.nmi_program_[0]; break;
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case ExecutionState::Phase::FetchDecode: target.scheduled_program_counter_ = &target.current_instruction_page_->fetch_decode_execute[0]; break;
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case ExecutionState::Phase::Operation: target.scheduled_program_counter_ = target.current_instruction_page_->instructions[target.operation_]; break;
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}
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target.scheduled_program_counter_ += execution_state.steps_into_phase;
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}
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// Boilerplate follows here, to establish 'reflection'.
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State::State() {
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if(needs_declare()) {
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DeclareField(registers);
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DeclareField(execution_state);
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DeclareField(inputs);
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}
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}
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State::Registers::Registers() {
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if(needs_declare()) {
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DeclareField(a);
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DeclareField(flags);
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DeclareField(bc);
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DeclareField(de);
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DeclareField(hl);
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DeclareField(bcDash);
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DeclareField(deDash);
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DeclareField(hlDash);
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DeclareField(ix);
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DeclareField(iy);
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DeclareField(ir);
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DeclareField(program_counter);
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DeclareField(stack_pointer);
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DeclareField(interrupt_mode);
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DeclareField(iff1);
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DeclareField(iff2);
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DeclareField(memptr);
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}
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}
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State::ExecutionState::ExecutionState() {
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if(needs_declare()) {
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DeclareField(is_halted);
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DeclareField(requests);
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DeclareField(last_requests);
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DeclareField(temp8);
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DeclareField(operation);
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DeclareField(temp16);
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DeclareField(flag_adjustment_history);
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DeclareField(pc_increment);
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DeclareField(refresh_address);
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AnnounceEnum(Phase);
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DeclareField(phase);
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DeclareField(half_cycles_into_step);
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DeclareField(steps_into_phase);
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DeclareField(instruction_page);
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}
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}
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State::Inputs::Inputs() {
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if(needs_declare()) {
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DeclareField(irq);
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DeclareField(nmi);
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DeclareField(bus_request);
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DeclareField(wait);
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}
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}
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